Chip Select Clock Synchronization for Wider 2N Timing Margin
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Solution Overview
Problem
In semiconductor memory devices, it is challenging to increase the set-up/hold margin of command/address signals in the 2N mode due to the limited holding period of the chip select (CS) signal, which is typically one clock period in the 1N mode.
Innovation Solution
The implementation of a CS gear down mode, where the holding period of the CS signal is increased to two cycles of the external clock signal, along with the use of an internal clock signal with a lower frequency than the external clock signal, to stabilize memory operations in the 2N mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the holding period of the chip select signal is increased to two clock periods in 2N mode, then the set-up/hold margin of command/address signals is improved, but the device complexity increases due to the need for CS gear down mode and internal clock signal generation
Solution Approach 1:
The patent implements dynamic clock signal generation where the internal clock signal frequency is adjusted based on the operating mode (1N or 2N). In 2N mode with CS gear down enabled, the internal clock frequency is set to half of the external clock frequency, allowing the CS signal to be held for two external clock periods. This dynamic frequency adjustment resolves the contradiction by providing extended hold time only when needed, rather than permanently increasing system complexity.
Solution Approach 2:
The patent changes the frequency parameter of the internal clock signal based on operational requirements. When CS gear down mode is activated in 2N mode, the internal clock frequency is changed to 0.5 times the external clock frequency. This parameter change enables the chip select signal to maintain its level for two external clock periods, thereby improving the set-up/hold margin without permanently complicating the device architecture.
2Reliability
If the frequency of the internal clock signal is reduced to half of the external clock signal frequency, then the pulse width is increased and set-up/hold margin is improved, but the productivity decreases due to slower clock operation
Solution Approach 1:
The system dynamically adjusts the internal clock frequency based on the operational mode. In normal 1N mode, the internal clock operates at the same frequency as the external clock to maintain high productivity. When 2N mode with CS gear down is enabled, the internal clock frequency is temporarily reduced to half to improve set-up/hold margin. This dynamic switching resolves the contradiction by maintaining high speed operation during normal tasks while enabling slower, more reliable operation only when extended hold time is required.
Solution Approach 2:
The patent employs periodic action by using the divided internal clock signal specifically for chip select signal holding during 2N mode operations, while the main data I/O operations continue to operate at the higher external clock frequency. This selective use of reduced-frequency clocking ensures that productivity is maintained for time-critical operations while achieving improved margins where needed.
Data Source
AI summary
A semiconductor device includes a chip select signal flip-flop configured to: latch a chip select signal in-sync with a first propagation clock signal, and output a first chip select enable signal, and latch the chip select signal in-sync with a second propagation clock signal having a phase opposite to a phase of the first propagation clock signal, and output a second chip select enable signal; and a clock control circuit configured to generate the first propagation clock signal and the second propagation clock signal based on a clock signal, and selectively output one of the first propagation clock signal and the second propagation clock signal based on an enable level of the first chip select enable signal and an enable level of the second chip select enable signal.