Chip Self-Diagnosis via Sequence Generation Circuit
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Solution Overview
Problem
Current methods for testing chips are labor-intensive and time-consuming, as they require manual detection of faults in scan chains and logic circuits, and cannot distinguish between scan chain and logic circuit failures when the chip is on a printed circuit board.
Innovation Solution
A chip design incorporating a sequence generation circuit, selection circuit, and scan chains that generate and respond to diagnosis sequences, allowing for automated error detection by comparing generated and output sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual testing methods are used to detect faults in scan chains and logic circuits, then fault detection can be performed, but the testing process becomes labor-intensive and time-consuming
Solution Approach 1:
The chip performs self-diagnosis by internally generating test sequences and comparing expected outputs with actual outputs. The sequence generation circuit produces diagnosis sequences that automatically flow through scan chains and logic circuits, with results captured and compared without external manual intervention, enabling the system to test itself
Solution Approach 2:
The diagnosis mechanism implements feedback by capturing actual output sequences from scan chains, comparing them against expected sequences generated by the sequence generation circuit, and using this comparison to identify faults. The control signal adjusts the scanning process based on this feedback to locate and characterize defects
2Reliability
If the chip is placed on a printed circuit board for testing, then basic functionality can be verified, but scan chain defects cannot be distinguished from logic circuit failures
Solution Approach 1:
The testing process is segmented into distinct phases: first testing logic circuits with function sequences, then testing scan chains with diagnosis sequences. This segmentation allows independent characterization of each component type, enabling precise fault localization to either logic circuits or scan chains based on which test phase reveals the defect
Solution Approach 2:
The sequence generation circuit and selection circuit are pre-configured within the chip to enable automatic switching between logic circuit testing and scan chain testing modes. This preliminary setup allows the chip to perform differentiated testing without requiring external reconfiguration, ensuring accurate fault identification from the outset
3Reliability
If automated test machines are used to completely scan logic circuits and scan chains, then comprehensive fault detection is achieved, but the testing process becomes even more time-consuming
Solution Approach 1:
The chip performs self-diagnosis by internally generating test sequences and comparing expected outputs with actual outputs. The sequence generation circuit produces diagnosis sequences that automatically flow through scan chains and logic circuits, with results captured and compared without external manual intervention, enabling the system to test itself
Solution Approach 2:
The same scan chains and logic circuits are used for both normal operation and automatic diagnosis, eliminating the need for separate dedicated test equipment. The selection circuit enables a single testing infrastructure to perform multiple functions: logic circuit testing, scan chain testing, and fault localization, all within the chip itself
Data Source
AI summary
A chip includes one or more function input pads, a sequence generation circuit, one or more logic circuits, one or more scan chains, a selection circuit, and one or more sequence output pads. The function input pad is configured to receive a function sequence. The sequence generation circuit is configured to generate a diagnosis sequence. The logic circuit includes a plurality of logic gates, for responding to the function sequence and outputting one or more logic results. When enabled by the selection circuit, the scan chain outputs a response result in response to the logic result or a diagnosis result in response to the diagnosis sequence. The sequence output pad receives the diagnosis result when the scan chain responds to the diagnosis sequence.