Electronic Chip Side Contacts for Visible Solder Inspection
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Solution Overview
Problem
Conventional surface mount chips lack the ability for visual inspection of solder joint quality, which is crucial in applications like automotive and medical fields where electrical connection reliability is paramount, and existing methods restrict miniaturization due to bulky connection metallizations.
Innovation Solution
The method involves forming metal contacts on the side of a semiconductor substrate, depositing protective resins, and creating trenches to expose these contacts laterally, allowing for visual inspection of solder joints without the need for bulky frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection metallizations are arranged on the lower face side of the chip, then the chip structure is compact, but visual inspection of solder joint quality becomes impossible
Solution Approach 1:
The patent moves the connection metallizations from the traditional lower face position to the lateral flanks of the chip, changing the spatial dimension of connection access. This dimensional shift allows solder joints to be accessible from the side, enabling visual inspection from above while maintaining compact chip structure.
Solution Approach 2:
The chip structure is segmented into distinct functional zones: the semiconductor substrate, the lateral connection metallizations on flanks, and the protective encapsulation. This segmentation allows the connection interface to be separated from the active circuit area, enabling independent optimization of inspection accessibility.
2Difficulty of detecting and measuring
If bulky connection metallizations are used for visual inspection, then solder joint inspection becomes possible, but chip miniaturization is restricted
Solution Approach 1:
Instead of extending metallizations bulky in the vertical dimension, the patent positions them laterally on the chip flanks. This dimensional repositioning provides inspection access without increasing chip thickness, enabling miniaturization while maintaining inspectability.
Solution Approach 2:
The connection metallizations are implemented as thin lateral extensions on the chip flanks rather than bulky three-dimensional structures. This thin-film approach provides sufficient surface area for solder joint formation and inspection while minimizing volume consumption.
3Difficulty of detecting and measuring
If metal contacts extend laterally beyond protective resin, then visual inspection is enabled, but manufacturing complexity increases
Solution Approach 1:
The protective resin is deposited to cover the semiconductor substrate and extend laterally, but is intentionally designed to stop before covering the metal contact extensions. This preliminary positioning of the resin layer simplifies subsequent steps by pre-establishing the exposure zones for visual inspection.
Solution Approach 2:
The protective resin application exhibits local quality variation: it fully covers the semiconductor substrate for protection, but deliberately leaves the lateral metal contact regions exposed. This localized differentiation achieves both protection and inspection accessibility without requiring complex post-processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables easy visual inspection of solder joints, reduces chip thickness, and facilitates miniaturization while maintaining electrical connection reliability without expensive X-ray techniques.
Implementation Method 1
forming metal contacts on the side of a first face of a semiconductor substrate
Implementation Method 2
depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate
Data Source
AI summary
The present disclosure relates to a method for manufacturing electronic chips comprising, in order:a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate;c. forming first trenches of a first width on the side of a second face of the semiconductor substrate;d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate;e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; andf. forming third trenches opposite the second trenches, the third trenches extending through the metal contacts.