Semiconductor Chip Sidewall Recess for Reliable Wafer Dicing
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Solution Overview
Problem
Conventional wafer dicing methods using laser beams often damage semiconductor devices by melting not only the cut region but also surrounding areas, leading to reduced reliability of semiconductor chips.
Innovation Solution
The method involves manufacturing semiconductor chips using a wafer dicing process with improved reliability, featuring a base substrate with a stress relief region and modified layers in the scribe lane region, along with a recessed sidewall to minimize damage during the dicing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a laser beam is used to cut the semiconductor wafer by heating and melting, then the cutting process is efficient, but the surrounding region is melted and damaged, reducing device reliability
Solution Approach 1:
The laser beam is focused to create a narrow, localized modification region within the scribe lane, segmenting the energy deposition to avoid affecting surrounding devices. The modification is confined to a specific depth and lateral region, separating the cutting function from the device regions.
Solution Approach 2:
The laser beam creates a localized modified layer with different properties (amorphous or cracked structure) only in the scribe lane region, while leaving the chip regions with intact crystal structure and device functionality. This local modification achieves cutting without widespread thermal damage.
2Reliability
If the laser beam is focused deeply into the wafer to avoid surface damage, then device damage is reduced, but the cutting effectiveness decreases
Solution Approach 1:
A modified layer is formed in advance within the scribe lane region before the final separation step. This preliminary modification creates a weakened zone that facilitates clean separation, ensuring both device integrity and effective cutting.
Solution Approach 2:
The laser beam is focused at a specific depth within the wafer thickness to create the modified layer, utilizing the depth dimension to position the modification zone optimally. This controlled depth focusing allows the modified layer to form at the appropriate location for effective separation while protecting surface devices.
3Reliability
If multiple modified layers are formed in the scribe lane region, then separation reliability is improved, but the device layer may be affected by excessive processing
Solution Approach 1:
Multiple modified layers are formed as intermediary structures within the scribe lane region, acting as separation planes that facilitate clean wafer separation. These intermediary layers are confined to the scribe lane and do not directly affect the device layer, enabling reliable separation while protecting devices.
Solution Approach 2:
Each modified layer is created with localized properties only in the scribe lane region, ensuring that the multiplication of modified layers improves separation reliability without accumulating harmful effects in the device regions. The local confinement prevents processing impacts on the device layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor chips by reducing damage during the dicing process, ensuring the integrity of semiconductor devices and improving the overall manufacturing process.
Implementation Method 1
a stealth dicing process is used to induce internal cracks by focusing a laser beam onto the wafer
Data Source
AI summary
A semiconductor chip includes a base substrate including a first surface, a second surface opposite to the first surface, and a sidewall extending between the first surface and the second surface, and a device layer on the first surface of the base substrate, wherein the base substrate includes a stress relief region within a first depth from the second surface and a second depth from the sidewall, and at least a portion of the sidewall of the base substrate is recessed inward from the sidewall of the device layer.