Semiconductor Chip Stack Bonding Layout for High-Aspect-Ratio Packaging
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Solution Overview
Problem
Semiconductor chips with a high aspect ratio are difficult to appropriately dispose in semiconductor packages due to their elongated shape, leading to challenges in stacking and packaging, particularly as the aspect ratio increases, causing instability and making multi-stage stacking difficult.
Innovation Solution
The use of varying thickness bonding layers at the lower stages of semiconductor chip stacks allows for closer alignment and reduced package area by covering parts of the semiconductor chip and bonding wires, enabling more efficient disposition of high aspect ratio chips without the need for complex multi-stage stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high aspect ratio semiconductor chips are mounted in the package, then the chip density and functionality are improved, but the chips become difficult to appropriately dispose and stack
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking by varying bonding layer thicknesses. This enables high aspect ratio chips to be disposed in multiple layers vertically, increasing chip density while maintaining ease of operation through structured layering
Solution Approach 2:
Different bonding layers are assigned different thicknesses based on their specific positions and functions. Lower bonding layers have greater thickness to provide support and stability, while upper bonding layers have smaller thickness, enabling appropriate disposal of high aspect ratio chips at different locations
2Quantity of substance
If multi-stage stacking is attempted with high aspect ratio chips, then chip capacity is increased, but stability decreases and chips become prone to breakage
Solution Approach 1:
The patent changes the thickness parameter of bonding layers at different stages. Lower bonding layers have greater thickness to provide mechanical support and stability, while upper bonding layers have smaller thickness, allowing multi-stage stacking to increase chip capacity without compromising reliability
Solution Approach 2:
Thicker bonding layers are placed at lower stages before upper chips are mounted, providing cushioning and support that prevents chip breakage during handling and operation, thereby maintaining stability in multi-stage configurations
3Ease of manufacture
If uniform thickness bonding layers are used, then manufacturing simplicity is maintained, but package area increases and alignment efficiency decreases
Solution Approach 1:
The patent applies different bonding layer thicknesses at different positions (lower vs. upper stages) to optimize package area. This local differentiation enables closer alignment of chips in the vertical direction, reducing the overall package footprint while remaining manufacturable through controlled deposition processes
4Reliability
If thicker bonding layers are used throughout, then chip alignment and stability are improved, but package area increases
Solution Approach 1:
The patent optimizes bonding layer thickness by making lower bonding layers thicker for alignment and stability, while upper bonding layers are thinner to minimize package area. This parameter differentiation achieves reliable chip alignment without unnecessarily increasing the overall package footprint
Data Source
AI summary
A semiconductor device according to an embodiment includes a substrate, a first stack, a second stack, a first bonding layer, a second bonding layer, a first wire, and a second wire. The first stack has a plurality of first semiconductor chips. The second stack has a plurality of second semiconductor chips. The first bonding layer is provided at a lower part of each of the plurality of first semiconductor chips. The second bonding layer is provided at a lower part of each of the plurality of second semiconductor chips. The first wire electrically connects the first semiconductor chips and the second semiconductor chips to one another. The second wire electrically connects the substrate and the second semiconductor chips. The first bonding layer provided at the lower part of the first semiconductor chip in a lowest stage has a thickness different from the thickness of the other first bonding layers.