Chip Stack Conductive Plug Layout for Shorter Interconnect Paths
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to create smaller, more efficient packaging techniques for stacked semiconductor devices that reduce physical size while maintaining high performance and low power consumption.
Innovation Solution
A chip stack structure is formed by bonding two semiconductor wafers with conductive plugs that directly connect to the interconnect structure, bypassing the device layer, allowing for a shorter conductive path and improved signal and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding techniques are used to connect stacked semiconductor wafers, then the wafers can be bonded together, but the conductive path is long and resistance is high
Solution Approach 1:
The patent extracts the conductive plug formation process from the conventional bonding technique, creating direct conductive paths through the substrate that bypass the device layer. This separation of the conductive connection path from the conventional bonding interface reduces the overall conductive path length and resistance, thereby improving signal and power integrity between stacked semiconductor devices.
Solution Approach 2:
The conductive plugs are formed in the substrate before the semiconductor devices are stacked and bonded together. This preliminary action of creating the conductive pathways in advance allows for direct electrical connection between stacked devices, eliminating the need for longer conductive paths through the device layer and reducing resistance at the bonding interface.
2Volume of moving object
If semiconductor devices are stacked to reduce physical size, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the conductive connection path into two distinct parts: conductive plugs formed in the substrate and separate bonding interfaces between stacked devices. This segmentation allows the conductive pathways to be independently formed and optimized, simplifying the overall manufacturing process while enabling compact stacked device configurations that reduce physical size.
Solution Approach 2:
The conductive plugs act as intermediaries between the stacked semiconductor devices and the substrate, providing direct electrical connection without requiring complex routing through the device layers. This intermediary structure simplifies the packaging technique by creating straightforward vertical connections that reduce manufacturing complexity while maintaining small form factor.
3Reliability
If conductive plugs are formed to reduce resistance, then signal integrity improves, but additional manufacturing steps are required
Solution Approach 1:
The patent merges the conductive plug formation process with the existing substrate preparation and bonding processes. By integrating the conductive plug creation into the standard manufacturing flow rather than adding completely separate steps, the method reduces resistance and improves power integrity while minimizing the increase in manufacturing complexity.
Solution Approach 2:
The conductive plugs are formed using self-aligned processes where the plug locations are automatically positioned based on the device geometry and bonding interface requirements. This self-service approach reduces the need for additional alignment and positioning steps, making the manufacturing process more straightforward despite the added functionality of reduced resistance paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces resistance and enhances signal and power integrity between chips, improving the performance and stability of the chip package structure.
Implementation Method 1
a conductive plug penetrating through the insulating layer to the second interconnect structure... enhances signal and power integrity between chips
Data Source
AI summary
A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The first interconnect structure includes a first dielectric layer and a first bonding pad embedded in the first dielectric layer. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure, the second interconnect structure includes a second dielectric layer and a second bonding pad embedded in the second dielectric layer, the first bonding pad is connected to the second bonding pad, and the first dielectric layer is connected to the second dielectric layer. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.