Chip Stack Structure with Vertical Conductive Lines and Fluid Cooling
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Solution Overview
Problem
Current semiconductor package technologies face challenges in reducing the volume of semiconductor packages to meet the trend of 'light, thin, short, and small' electric products, as existing methods such as wire bonding and through-silicon via (TSV) do not effectively minimize horizontal and vertical distances between chips.
Innovation Solution
A chip stack structure is formed using a vertical conductive line disposed outside the projection area of chips, with each chip placed in an insulating film and connected through horizontal conductive lines, allowing for reduced size and efficient heat dissipation via a fluid in hollow channels within the insulating films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wire bonding or through-silicon via (TSV) methods are used to connect chips, then electrical connection between chips is achieved, but the horizontal and vertical distances between chips cannot be minimized, resulting in larger package volume
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacked configuration, connecting chips vertically through conductive lines extending from chip edges. This dimensional change enables compact stacking while maintaining electrical connectivity, directly reducing package volume without increasing inter-chip distances
Solution Approach 2:
Multiple chips are stacked in a nested configuration where each chip is positioned above the previous one, with conductive lines penetrating through insulating films to establish electrical connections between stacked layers. This nesting approach maximizes space utilization and minimizes overall package footprint
2Volume of moving object
If chip stacking is implemented to reduce package volume, then horizontal space is saved, but heat dissipation becomes more challenging due to increased density
Solution Approach 1:
Thermal interface materials are introduced as intermediaries between stacked chips to facilitate heat transfer. These materials fill the gaps and contact interfaces between chips, enabling efficient thermal conduction pathways that prevent heat accumulation in the dense stacked structure
Solution Approach 2:
The patent incorporates fluid-filled channels within the package structure to enable active heat dissipation. The fluid circulates through these channels, absorbing heat from the stacked chips and transporting it away, thereby managing thermal load in the compact configuration
3Area of stationary object
If vertical conductive lines are disposed outside the projection area of chips, then electrical connection is achieved with reduced horizontal space, but manufacturing complexity increases
Solution Approach 1:
The conductive lines are formed extending from chip edges before the stacking process occurs. This preliminary preparation of conductive pathways simplifies the subsequent assembly process, as the electrical connections are already in place and only require alignment and connection to corresponding pads on adjacent chips
Solution Approach 2:
The electrical connection system is segmented into discrete conductive lines positioned at chip edges rather than requiring comprehensive inter-chip wiring. This segmentation allows for simplified manufacturing where only specific connection points need to be established between stacked chips, reducing overall manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size and thickness of the chip stack structure while enabling effective electrical connection and heat management, addressing the volume reduction and heat dissipation challenges in semiconductor packages.
Implementation Method 1
heat management
Implementation Method 2
heat dissipation via a fluid in hollow channels
Data Source
AI summary
A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a plurality of chips, a vertical conductive line, a plurality of insulating films and a fluid. The chips are overlapped. The vertical conductive line is electrically connected to some of the chips. The vertical conductive line is disposed at the outside of a projection area of some of the chips. Each chip is disposed in one of the insulating films. The channels which are hollow are formed in one of the insulating films. The fluid is disposed in the channels.