Semiconductor Chip Stack Interconnect Layout for Low-Resistance Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electric and reliability characteristics.
Innovation Solution
The semiconductor device incorporates a substrate with a logic cell region and a connection region, featuring a dummy transistor, an intermediate connection layer, an etch stop layer, and a penetration contact that protrudes above the etch stop layer, with a first metal layer including interconnection lines and vias that directly connect to the intermediate connection layer, enhancing electrical connectivity and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern size, then pattern size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent introduces penetration contacts that extend vertically through multiple interlayer insulating layers to directly contact the active region, adding a vertical dimension to the connection path. This three-dimensional approach compensates for the reduced horizontal scaling by providing direct electrical pathways that bypass the limitations of scaled-down planar transistor dimensions, thereby maintaining operational properties despite smaller pattern sizes.
Solution Approach 2:
The penetration contact acts as an intermediary element that directly connects the first metal layer to the active region, eliminating the need for intermediate connection layers and vias that would otherwise be required in scaled-down devices. This intermediary structure provides a reliable electrical pathway that maintains signal integrity and reduces resistance in miniaturized devices.
2Ease of manufacture
If conventional interconnection structures are used in scaled-down devices, then manufacturing is simpler, but electrical resistance increases
Solution Approach 1:
The penetration contact extends vertically through the interlayer insulating layers to directly reach the active region, creating a short electrical pathway in the vertical dimension. This approach reduces the total resistance by minimizing the horizontal routing distance while maintaining a manufacturing process that integrates with existing semiconductor fabrication techniques.
3Reliability
If penetration contact protrudes above etch stop layer, then contact area is increased, but device complexity increases
Solution Approach 1:
The penetration contact structure merges multiple functions into a single element: it serves as both the electrical connection pathway through the interlayer insulating layers and the contact pad that interfaces with the active region. The protrusion above the etch stop layer combines the through-contact function with the surface contact function, eliminating the need for separate contact structures and reducing overall device complexity despite the enhanced contact area.
Data Source
AI summary
A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.