Semiconductor Chip Stack Protection Ring and Metal Pillar Cavity
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Solution Overview
Problem
Conventional packaging methods for semiconductor devices like surface acoustic wave devices and micro-electro-mechanical devices often compromise the structural integrity and performance of these devices due to direct contact with packaging materials, leading to insufficient structure strength and impaired functionality.
Innovation Solution
A chip stack design featuring stacked chips with metal pillars and protection rings made of materials like Cu, Au, and Sn, which form gaps and cavities to prevent packaging material contact, ensuring the devices' performance and structural integrity by using materials such as glass, LiTaO3, and SiC for substrates and SU8 photoresist for protection rings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a cavity is formed around the acoustic wave device using conventional SU8 photoresist layers, then the packaging material is prevented from contacting the device, but the structure strength becomes insufficient causing the photoresist layers to concave down
Solution Approach 1:
The patent uses a composite structure combining sacrificial layer, SU8 photoresist layers, and support structures (such as metal pillars or reinforcement elements). This composite approach allows the cavity to maintain structural strength while preventing packaging material contact, resolving the contradiction between protection and structural integrity.
Solution Approach 2:
The cavity structure is segmented into multiple functional layers: a sacrificial layer for cavity formation, SU8 photoresist layers for sealing, and support structures for reinforcement. This segmentation allows each layer to perform its specific function optimally, with support structures providing the necessary strength to prevent concavity.
2Adaptability or versatility
If the area of the acoustic wave device is increased, then the device functionality is improved, but the area of the cavity increases causing insufficient structure strength
Solution Approach 1:
The patent introduces vertical support structures (metal pillars or reinforcement elements) into the cavity, adding a vertical dimension of support. This allows the cavity to span larger horizontal areas without compromising structural strength, enabling larger device areas while maintaining structural integrity.
Solution Approach 2:
The combination of SU8 photoresist with higher strength support materials creates a composite cavity structure that can accommodate larger device areas. The support structures distribute the mechanical load across the expanded cavity area, preventing concavity even as the device area increases.
3Device complexity
If the first SU8 photoresist layer directly contacts the acoustic wave device, then the cavity structure is simplified, but the device performance is negatively impacted
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary between the acoustic wave device and the SU8 photoresist layer. This sacrificial layer is removed to form the cavity, ensuring that the SU8 photoresist does not directly contact the device. This intermediary approach protects device performance while maintaining a manageable cavity structure.
Data Source
AI summary
A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.