Chip Stack Recess Structure for Wiring Layer Protection

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing chip-stacked devices face defects due to breakage of the outer peripheral region of the chip, primarily caused by fragments or foreign matter entering the gap between the chips and pressing against the wiring layers during bonding, leading to potential damage.

Innovation Solution

The introduction of a recessed portion in the outer peripheral surface of one chip, along with other structural modifications such as steps, softer outer peripheral members, or insulating layers, to prevent fragments from being pressed against the wiring layers, thereby reducing the risk of breakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal-to-metal bonding is used to stack chips, then electrical connection between chips is achieved, but fragments or foreign matter can enter the gap between chips and press against wiring layers causing breakage

Engineering Contradiction:

Improvedefect reductionVSAvoidfragment pressure on wiring layer

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A resin layer is provided between the first chip and second chip in the gap region to cushion and absorb the pressure from fragments or foreign matter before they can press against the wiring layers. This preliminary protective measure prevents direct contact between harmful factors and the wiring layer, reducing the risk of breakage while maintaining effective electrical connection through the connection portions.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The resin layer acts as an intermediary substance between the first chip and second chip, specifically in the gap region surrounding the connection portions. This intermediary material prevents direct pressure transmission from fragments to the wiring layer, while still allowing the connection portions to establish electrical connection between the chips.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If connection portions are provided between array surfaces for electrical connection, then chip stacking is enabled, but the outer peripheral region becomes vulnerable to fragment-induced breakage

Engineering Contradiction:

Improvewiring layer integrityVSAvoidouter peripheral region strength

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The resin layer is selectively provided in the gap region between chips, creating local protection where it is most needed - in the outer peripheral region surrounding the connection portions. This local quality approach strengthens the vulnerable outer peripheral area without affecting the electrical connection function in the array region, where the connection portions maintain wiring layer integrity.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20260082920A1Chip-stacked device

Publication Date: 2026.03.19 NUFLARE TECH INC

AI summary

A first chip includes a first substrate which includes a first outer peripheral surface and a first array surface surrounded by the first outer peripheral surface, and a first wiring layer provided on the first substrate. A second chip including a second substrate which includes a second outer peripheral surface facing the first outer peripheral surface and a second array surface facing the first array surface, which is surrounded by the second outer peripheral surface, and a second wiring layer provided on the second array surface. A plurality of connection portions is provided between the first array surface and the second array surface. The plurality of connection portions is configured to electrically connect the first wiring layer and the second wiring layer. The second substrate includes a recessed portion provided in the second outer peripheral surface.