Chip Stack Package Via Electrode Material Segmentation

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Solution Overview

Problem

Chip stack packages face deteriorated electrical characteristics due to the use of through via electrodes for connecting chips, which affects the reliability and efficiency of semiconductor products.

Innovation Solution

The use of different materials and diameters for power supply, ground, and signal transfer through via electrodes, with copper for power and ground electrodes and polycrystalline silicon doped with impurities for signal transfer electrodes, improves electrical characteristics by reducing inductance, resistance, and capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through via electrodes are used to connect chips in a chip stack package, then electrical connection between chips is achieved, but electrical characteristics deteriorate

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidthrough via electrode structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The through via electrodes are segmented into different types (power supply, ground, signal transfer) with different materials and dimensions. This segmentation allows each type to be optimized for its specific function, resolving the contradiction by improving electrical characteristics through specialized design while maintaining the necessary connectivity structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the chip stack package have different via electrode properties. Power supply and ground vias use copper with larger cross-sections for low resistance, while signal transfer vias use polycrystalline silicon with smaller cross-sections for low capacitance. This local quality differentiation improves overall electrical characteristics by matching via properties to functional requirements.

Inventive Principle:
Principle #3Local quality

2Reliability

If single material is used for all through via electrodes, then manufacturing is simplified, but electrical performance is compromised

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent employs composite materials strategy by using copper for power supply and ground through via electrodes, and polycrystalline silicon for signal transfer through via electrodes. This multi-material approach optimizes electrical performance (low resistance for power/ground, low capacitance for signal) while the manufacturing process is managed through sequential formation steps that accommodate different material requirements.

Inventive Principle:
Principle #40Composite materials

3Reliability

If uniform cross-section size is used for all through via electrodes, then fabrication is simplified, but electrical characteristics are degraded

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidvia electrode dimension control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The via electrodes have different cross-section sizes optimized for their specific functions. Power supply and ground vias have larger cross-sections to reduce resistance, while signal transfer vias have smaller cross-sections to reduce capacitance. This local quality differentiation improves electrical characteristics by matching via dimensions to functional requirements, with manufacturing precision maintained through controlled fabrication processes.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances noise and signal transfer characteristics while reducing manufacturing costs by allowing smoother current flow and improved signal transfer, leading to more reliable and efficient semiconductor products.

Implementation Method 1

the power supply through via electrode and the ground through via electrode are each formed of copper

Methodology Applied
Scientific EffectElectrical Conduction: Conduction (electrical)

Implementation Method 2

the signal transfer through via electrode is formed of polycrystalline silicon doped with impurities

Methodology Applied
Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS8446016B2Chip stack package
Publication Date: 2013.05.21 SAMSUNG ELECTRONICS CO LTD
  • US8446016B2 patent drawing
  • US8446016B2 patent drawing
  • US8446016B2 patent drawing

AI summary

A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.