Semiconductor Chip Stack Interconnect With Via-Free Penetration Contact
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electric and reliability characteristics.
Innovation Solution
The semiconductor device incorporates a substrate with a logic cell region and a connection region, featuring a dummy transistor, an intermediate connection layer, an etch stop layer, and a penetration contact that protrudes above the etch stop layer, directly connecting to a first metal layer interconnection line without a via, reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for small pattern size, then pattern size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D MOS-FET structures to three-dimensional vertically stacked transistor structures. By stacking multiple active patterns and gate electrodes vertically, the device achieves higher integration density while maintaining larger effective channel areas, thus improving operational properties despite reduced footprint.
Solution Approach 2:
The patent implements nested structures where gate electrodes wrap around active patterns in a FinFET configuration, and multiple transistor layers are stacked within a compact vertical space. This nesting allows larger effective device area to be contained within a smaller planar footprint, maintaining performance while reducing pattern size.
2Ease of manufacture
If conventional interconnection structures are used with vias, then manufacturing is simpler, but electrical resistance increases
Solution Approach 1:
The patent removes the via structure from the interconnection path between penetration contacts and metal interconnection lines. By establishing direct contact between the penetration contact and the metal interconnection line, the unnecessary via layer and its associated contact resistance are eliminated, reducing overall electrical resistance.
Solution Approach 2:
The patent segments the interconnection structure into distinct functional zones: penetration contacts extending through the substrate, intermediate connection layers for lateral routing, and metal interconnection lines for signal transmission. This segmentation allows optimization of each segment's properties, including direct contact interfaces that minimize resistance.
3Manufacturing precision
If etch stop layer covers the entire top surface, then manufacturing precision is improved, but contact area between penetration contact and metal layer is reduced
Solution Approach 1:
The patent applies the etch stop layer selectively rather than uniformly across the entire top surface. The etch stop layer is positioned to cover specific regions requiring precision control during etching, while leaving other regions exposed to allow direct contact between penetration contacts and metal interconnection lines, thus maintaining both manufacturing precision and adequate contact area.
Data Source
AI summary
A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.