Intermediate Chip Substrate for Thermal Isolation of Wirebonded Assemblies

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Solution Overview

Problem

Chip assemblies experience detrimental thermal load transfer from external devices, which can impair detector performance, and existing cooling methods often require large and costly cooling sources to mitigate this issue effectively.

Innovation Solution

A modified chip substrate configuration with a base substrate and an intermediate substrate, where the intermediate substrate has lower thermal conductivity than the base substrate, and is wirebonded to the base substrate and an external device, reducing thermal load transfer through the use of materials like steatite, yttria, and cordierite, and incorporating a gap between substrates to further minimize heat transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a cooling source is provided within the dewar container to cool the chip assembly, then the thermal load transfer is mitigated, but the size and thermal capacity of the cooling source must be large

Engineering Contradiction:

Improvechip assembly temperatureVSAvoidcooling source size

Core Design Contradiction:

TemperatureVSVolume of stationary object

Solution Approach 1:

An intermediate substrate is introduced between the base substrate and the external environment. This intermediate substrate acts as a thermal barrier with lower thermal conductivity, reducing heat transfer from external devices to the chip assembly without requiring a large cooling source. The intermediate substrate mediates the thermal interaction while maintaining electrical connectivity through wirebond connections.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The substrate assembly uses composite construction with at least two different substrate materials having different thermal conductivities. The base substrate provides structural support and electrical connectivity, while the intermediate substrate provides thermal isolation. This composite approach allows optimization of thermal and electrical properties separately, reducing the need for large cooling capacity.

Inventive Principle:

Principle #40Composite materials

2Reliability

If wirebond connection is used to electrically couple the feedthrough device to the substrate, then electrical connectivity is achieved, but thermal load transfer occurs between the external device and the detector

Engineering Contradiction:

Improveelectrical couplingVSAvoidthermal load transfer

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The intermediate substrate serves as a mediator that allows electrical connectivity while blocking thermal transfer. The wirebond connections pass through or connect to the intermediate substrate, which has lower thermal conductivity than the base substrate. This intermediary structure enables the electrical function to be maintained while the harmful thermal effect is reduced through the intermediate thermal barrier.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces thermal load transfer by approximately 50% compared to conventional substrates, enabling faster cool-down times and allowing for smaller, less costly cooling solutions.

Implementation Method 1

a material of the base substrate has a first thermal conductivity and a material of the intermediate substrate has a second thermal conductivity that is lower than the first thermal conductivity

Methodology Applied

Scientific EffectThermal conductivity: Conduction (thermal)

Implementation Method 2

Each of the plurality of intermediate circuit traces are wirebonded to a respective one of the plurality of base circuit traces

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11882659B2Chip substrate for reducing thermal load on a chip assembly mounted thereon

Publication Date: 2024.01.23 RAYTHEON CO

AI summary

A chip substrate includes a base substrate having a plurality of base circuit traces mounted thereon for supporting a chip assembly and an intermediate substrate mounted on the base substrate adjacent the plurality of base circuit traces. The intermediate substrate has a plurality of intermediate circuit traces mounted thereon. Each of the plurality of intermediate circuit traces are wirebonded to a respective one of the plurality of base circuit traces and the plurality of intermediate circuit traces are configured to be electrically coupled to an external device. For example, each of the plurality of intermediate circuit traces may be wirebonded to a respective one of a plurality of feedthrough circuit traces mounted on a feedthrough device.