Semiconductor Chip Packaging Substrate Via Sharing
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Solution Overview
Problem
The existing flip chip technique faces challenges in achieving high-density solder-including electrode arrangements in the central part of semiconductor chips, leading to voltage drops due to wiring resistance and limitations in miniaturization and signal density.
Innovation Solution
A semiconductor device with a packaging substrate featuring a continuous solder resist layer and apertures that expose wiring surfaces, allowing for the placement of solder-including electrodes with alternating electric potentials, reducing the number of vias and increasing electrode density while minimizing voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via is provided for each pillar bump in the central part, then power supply reliability is improved, but the number of pillar bumps that can be disposed is limited
Solution Approach 1:
Multiple pillar bumps sharing a single via: The patent allows multiple pillar bumps (first and second pillar bumps) to share a common via, rather than providing a dedicated via for each pillar bump. This merging approach increases the number of pillar bumps that can be disposed in the central part while maintaining power supply reliability through the shared via connection.
Solution Approach 2:
The via serves multiple functions: It provides electrical connection for power supply to multiple pillar bumps simultaneously, and acts as a common connection point for both first and second pillar bumps. This multi-functionality allows the via to support multiple electrode connections without requiring separate vias for each electrode.
2Reliability
If solder bumps are made larger to ensure gap for underfill resin injection, then underfill injection is improved, but inter-terminal pitch increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical arrangement by using pillar bumps with height. This allows the underfill resin to be injected through the via from the bottom side, utilizing the vertical dimension to ensure proper gap and injection while maintaining small inter-terminal pitch in the horizontal plane.
Solution Approach 2:
The via acts as an intermediary structure that facilitates underfill resin injection. By providing a dedicated via that extends through the substrate, the patent creates a controlled pathway for underfill injection that ensures proper gap maintenance without requiring larger solder bumps, thus enabling fine inter-terminal pitch.
3Reliability
If pillar bumps are disposed in the central part, then voltage drop is reduced, but wiring resistance becomes a problem
Solution Approach 1:
The patent extracts the electrical connection function from the horizontal wiring plane and moves it to the vertical dimension through vias. By providing vias that extend from the front surface through the substrate to the rear surface, the electrical connection is established in the vertical direction, reducing the horizontal wiring distance and associated resistance that would cause voltage drop.
Solution Approach 2:
The patent utilizes the vertical dimension by implementing pillar bumps with height and corresponding vias that extend through the substrate thickness. This three-dimensional arrangement reduces the horizontal wiring distance in the central part, thereby reducing wiring resistance and voltage drop while maintaining effective power supply to the pillar bumps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-density solder-including electrode placement, reduces voltage drops, and supports miniaturization, enhancing power supply efficiency and reliability in semiconductor devices.
Implementation Method 1
The plurality of solder-including electrodes 130 are connected to the plurality of wirings 150
Implementation Method 2
An underfill resin 40 may be provided between the semiconductor chip 10 and the packaging substrate 20
Data Source
AI summary
A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.