Chip Test System Signal Line Segmentation for Multi-Chip Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing chip test methods are limited by the inability to simultaneously read multiple tested chips due to restricted input/output interfaces, reducing test efficiency and the number of chips that can be tested.
Innovation Solution
A chip test system with m sets of first signal lines and m*n sets of second signal lines, allowing each chip test site to be coupled to both, enabling simultaneous testing of multiple chips by activating chip selection signal lines and outputting instructions and data through the appropriate signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If one chip selection signal line controls one row or column of tested chips, then individual control of chips is achieved, but the number of chips that can be simultaneously tested is limited due to limited I/O interfaces
Solution Approach 1:
The patent divides the chip array into multiple rows and columns, with each row having its own chip selection signal line and each column having its own physical signal lines. This segmentation allows different combinations of row and column selections to address individual chips or groups of chips, enabling both individual control and simultaneous testing of multiple chips through coordinated activation of selection lines.
Solution Approach 2:
The patent makes the chip selection signal lines and physical signal lines serve multiple functions. The same set of signal lines can be used to control different chips at different times, and can simultaneously serve multiple chips when activated in combination. This multi-functionality increases the number of testable chips without requiring additional I/O interfaces.
2Productivity
If limited pins are used to implement simultaneous write on multiple tested chips, then write operation is achieved, but simultaneous read on multiple tested chips cannot be implemented
Solution Approach 1:
The patent implements dynamic control of signal line activation based on the test operation type. During write operations, chip selection signal lines are activated to enable simultaneous writing to multiple chips. During read operations, the same signal lines are dynamically reconfigured and activated to enable simultaneous reading from multiple chips. This dynamic reconfiguration allows the system to adapt to different operation requirements using the same physical resources.
Data Source
AI summary
The present invention provides a chip test method, apparatus, device, and system. The chip test system may include: a test equipment, including n chip selection signal lines, m sets of first signal lines, and m*n sets of second signal lines; and m*n chip test sites, wherein each chip test site may be coupled to one of the n chip selection signal lines and one of the m sets of first signal lines, each of the m*n chip test sites may correspond to a unique combination of a chip selection signal line and a first signal line coupled thereto, and each chip test site may be correspondingly coupled to one of the m*n sets of second signal lines. According to an embodiment of the present invention, the limited pins of a test equipment may be used to implement individual control of multiple chips.