Integrated Circuit Via Randomization for Stable Chip Individualization

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Solution Overview

Problem

Existing methods for individualizing integrated circuits are sensitive to environmental variations and aging, leading to reduced robustness and potential misidentification of legitimate circuits as counterfeit.

Innovation Solution

A method is developed to create a random and unique individualization zone on microelectronic chips by randomly degrading via connections using particles deposited on a dielectric layer, forming functional and dysfunctional vias, which are then filled with conductive material, resulting in a response that is stable over time and difficult to clone.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If functional dispersions of integrated circuits are used for individualization, then unique identification is achieved, but sensitivity to environmental variations and aging increases

Engineering Contradiction:

Improveindividualization robustnessVSAvoidenvironmental sensitivity

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of environmental sensitivity into a beneficial feature by intentionally degrading vias during manufacturing. The random degradation pattern creates a unique fingerprint that is stable over time, transforming the vulnerability to environmental changes into a robust individualization mechanism that does not depend on environmental conditions.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent applies preliminary action by deliberately degrading vias during the manufacturing process before the integrated circuit is deployed. This pre-established degradation pattern creates a stable individualization signature that remains constant throughout the device's operational life, eliminating the need to rely on environmental variations that change over time.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If vias are deliberately and randomly degraded using diblock polymer particles, then individualization is achieved, but the openings in the etching mask are not satisfactorily sealed

Engineering Contradiction:

Improveindividualization effectivenessVSAvoidmask opening sealing quality

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the parameter of particle material from diblock polymer to metal particles. This material substitution fundamentally alters the degradation mechanism, allowing for effective via degradation while maintaining satisfactory sealing of mask openings, as metal particles provide the necessary structural integrity and adhesion properties that polymer particles lack.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method produces a unique and stable response for each integrated circuit, resistant to environmental changes and cloning, reducing the risk of misidentification and enhancing security.

Implementation Method 1

randomly depositing particles on an exposed face of the dielectric layer

Methodology Applied

Scientific EffectRandom deposition: Deposition (physical)

Implementation Method 2

applying a stirring pad to said exposed face so that the stirring pad moves at least some particles on the exposed face of the dielectric layer

Methodology Applied

Scientific EffectMechanical stirring: Stirring

Implementation Method 3

forming in the lithography layer patterns of openings

Methodology Applied

Scientific EffectPhotolithography: Photography

Implementation Method 4

etching the at least one dielectric layer through the mask openings, so as to form via openings

Methodology Applied

Scientific EffectEtching: Ablation

Implementation Method 5

filling the via openings with an electrically conductive material so as to form at least the vias of the interconnection level

Methodology Applied

Scientific EffectConductive material deposition: Deposition (physical)

Data Source

PatentEP4280275A1Method for producing an individualization zone of an integrated circuit

Publication Date: 2023.11.22 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Figure 1A~1B
Figure 2A~2B
Figure 3A~3B

AI summary

The invention relates to a method for creating an individualization zone of a microelectronic chip comprising a first (10A) and a second (20A) level of electrical traces (10, 20), and a level (30A) of interconnections including vias (30), the method comprising the following steps: • providing the first level (10A) and a dielectric layer (200), • randomly depositing particles (P) onto the dielectric layer (200), • depositing an etching mask (300) onto the dielectric layer (200) and the particles (P), • planarizing to obtain a composite layer (300') comprising the particles (P), • forming a lithography layer (400) comprising aperture patterns (401), • etching the composite layer through the aperture patterns (401) to form mask apertures (301, 301F), and then etching the dielectric layer (200) through mask openings (301, 301F),in order to obtain functional via openings (320) and degraded via openings (320F), • fill the via openings (320, 320F) so as to form the vias (30) of the interconnection level (30A), said vias (30) comprising functional vias (30OK) at the level of the functional openings (320) and dysfunctional vias (30KO) at the level of the degraded openings (320F).