Chip View Visualization for Circuit Design Revision Analysis
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Solution Overview
Problem
Current computer-aided design tools for integrated circuits, such as FPGAs, lack sufficient insight into how optimization options, settings, and resource placements influence circuit design outcomes like timing and power consumption, making it difficult to determine the most desirable combination for meeting design criteria.
Innovation Solution
A software-based chip view visualization tool that overlays various circuit design revisions, allowing designers to analyze and compare properties like timing, power, and compilation results, providing a virtual representation of physical chip implementations to understand the impact of optimization options and resource placements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple revisions are generated using computer-aided design tools with various optimization options, then the number of available circuit design choices increases, but the difficulty of analyzing and comparing these revisions increases
Solution Approach 1:
The patent transitions from traditional tabular reporting to a spatial visualization dimension by overlaying multiple circuit revisions onto a unified chip view. This allows designers to compare register placements, routing paths, and resource allocations across different revisions simultaneously in a spatial context, making the analysis of multiple revisions more intuitive and manageable.
Solution Approach 2:
The chip view visualization serves as an intermediary representation that mediates between the raw revision data and the designer's analytical process. By providing a unified visual framework that accommodates multiple revisions with different optimization options, the system enables easier comparison and selection of the most desirable circuit design configuration.
2Quantity of substance
If tabular reporting capabilities are used to compare revisions, then the quantity of revision data that can be displayed increases, but the insight into how optimization options influence outcomes decreases
Solution Approach 1:
The patent transforms the data presentation from a one-dimensional tabular format to a two-dimensional spatial visualization. By mapping revision data onto the physical chip layout, the system preserves the quantity of detailed revision information while adding spatial context that reveals relationships between optimization options and outcomes, such as how register placement affects timing and resource utilization.
3Speed
If register retiming is performed to improve maximum clock signal frequency, then the performance of the circuit design improves, but the complexity of the circuit design increases
Solution Approach 1:
The patent enables dynamic comparison of different register retiming configurations by visualizing multiple revisions on a unified chip view. Designers can interactively examine how different register placements and retiming strategies affect the maximum clock frequency and overall circuit performance, allowing them to select the optimal balance between speed improvement and design complexity.
Data Source
AI summary
A method includes receiving a first circuit design, deriving circuit design revisions based on the first circuit design, receiving revision information for each of the circuit design revisions that is output as a result of compilation of the circuit design revisions, extracting location information, timing information, or both for resources from the revision information, for each of the circuit design revisions, mapping the resources into a chip view based on the location information, the timing information, or both. The chip view includes a virtual visualization of an actual physical chip and the resources are mapped to their actual locations on the virtual visualization as they would be implemented on the actual physical chip. The method also includes generating the chip view of the circuit design revisions that displays a report specific to one or more properties of the circuit design revisions.