Chip-to-Wafer Lamination Using Thermal Expansion Shim Alignment
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Solution Overview
Problem
Conventional Chip-to-Wafer bonding methods require repetitive positioning, heating, and press-fitting processes for each chip, leading to low throughput and increased manufacturing time and cost, especially as miniaturization advances.
Innovation Solution
The Chip-to-Wafer chip lamination technique uses a cavity to accommodate and position multiple chips simultaneously, employing a shim with a higher Coefficient of Thermal Expansion than the cavity material to achieve automatic high-precision alignment through thermal deformation, allowing for batch processing and reducing the number of necessary steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional Chip-to-Wafer bonding is used with repetitive positioning and heating for each chip, then positioning precision can be achieved, but manufacturing throughput is low and processing time is long
Solution Approach 1:
Multiple chips are positioned and bonded simultaneously in a single heating process within a cavity structure, merging multiple sequential operations into one parallel operation. This increases throughput while maintaining positioning precision through the cavity's geometric constraints and shim-based alignment mechanism.
Solution Approach 2:
Chips are pre-positioned within the cavity using shims before the actual bonding process. The shims are inserted to establish precise geometric relationships among chips and between chips and the substrate, enabling automatic alignment without repetitive positioning steps during bonding.
2Quantity of substance
If multiple chips are laminated using conventional methods, then chip integration is achieved, but the number of process steps increases and manufacturing cost increases
Solution Approach 1:
Multiple chip lamination operations are combined into a single batch processing step. All chips within the cavity are heated and bonded simultaneously to the substrate, reducing the number of repetitive process steps from N (for N chips) to 1, thereby simplifying the manufacturing process and reducing costs.
Solution Approach 2:
The cavity structure serves multiple functions: it holds multiple chips, provides positioning references, maintains geometric relationships, and enables simultaneous heating. This multi-functionality allows high-volume lamination without increasing process complexity.
3Manufacturing precision
If chips are positioned manually or with complex positioning mechanisms, then alignment precision is maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The system uses self-aligning features where chips automatically position themselves relative to the cavity walls and shims during insertion. The geometric constraints of the cavity and the deformation characteristics of the shims create automatic alignment without requiring external positioning mechanisms or complex control systems.
Solution Approach 2:
The shims are made of material with higher thermal expansion coefficient than the cavity. During heating, the shims expand and deform to push chips against the cavity walls, achieving precise alignment automatically through thermal deformation rather than mechanical positioning mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly enhances manufacturing throughput and reduces costs by enabling low-cost, high-precision, simultaneous lamination of multiple chips, with processing time reduced by up to 1/128 times compared to conventional methods.
Implementation Method 1
The shim material has a larger coefficient of thermal expansion than that of the cavity material... The one or more shims are expanded and deformed at the temperature. The deformed one or more shims push and align the one or more chips to the inner walls of the array of one or more cavities.
Data Source
AI summary
This embodiment addresses a novel Chip-to-wafer chip lamination technique that provides low cost and high throughput. In the Chip-to-Chip process, using the temperature rise and utilizing deformation caused by thermal expansion of a metal shim inserted between the inner wall of a cavity, in which multiple chips are laminated and accommodated, multiple chips in the cavity are pressed against a reference surface on a side wall of the cavity to automatically perform positioning.