Chip-on-Wafer Package Via Last Process 3D Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and increasing integration density, requiring innovative packaging techniques for semiconductor devices, particularly in achieving smaller form factors, higher performance, and lower power consumption, which existing bonding methods and packaging techniques struggle to address effectively.
Innovation Solution
The via last process is employed for bonding semiconductor wafers, allowing for the formation of narrower, taller vias with improved aspect ratios, enabling more compact packaging and efficient electrical connections between stacked semiconductor devices through self-aligning spacers and dual damascene techniques, facilitating the creation of 3D integrated circuits with enhanced connectivity and reduced warpage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional bonding methods are used to package semiconductor devices, then the packaging process is simpler, but the form factor cannot be sufficiently reduced and integration density is limited
Solution Approach 1:
The patent transitions from conventional 2D packaging to 3D stacked packaging, where multiple semiconductor wafers are bonded vertically to form a three-dimensional structure. This dimensional change enables significant reduction in form factor while increasing integration density, as devices are arranged in the vertical dimension rather than only lateral expansion
Solution Approach 2:
The packaging process is divided into multiple discrete steps including wafer bonding, via formation, spacer deposition, and planarization. This segmentation allows each step to be optimized independently, managing the overall complexity through structured process breakdown while achieving the desired 3D integration
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
Self-aligning spacers are formed before via etching, establishing precise via locations and dimensions in advance. This preliminary action ensures that vias are automatically positioned with high precision relative to underlying features, meeting the stringent manufacturing precision requirements needed for reduced minimum feature sizes and increased integration density
3Volume of moving object
If stacked semiconductor wafers are bonded to reduce form factor, then device size decreases, but warpage control becomes more difficult
Solution Approach 1:
The patent employs planarization processes that modify the physical parameters of the stacked wafer structure, including applying pressure and heat to flatten warpage. By changing these physical parameters during processing, the structural stability is maintained despite the reduced form factor achieved through stacking
Data Source
AI summary
A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.