Semiconductor Chip Wiring Layout for Thermal Stress Isolation
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Solution Overview
Problem
Existing semiconductor devices face reliability issues under high voltage and large current conditions due to thermal stress and potential electrical contact failures between semiconductor chips and electrodes during pressure-welding.
Innovation Solution
Incorporation of conductive metal buffers and insulating films to alleviate thermal stress and prevent direct electrical contact between emitter wirings and gate wirings, enhancing the reliability of semiconductor chips and devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pressure-welding is applied to maintain electric contact under high voltage and large current, then power density and reliability are improved, but thermal stress and electrical contact failures occur
Solution Approach 1:
A buffer layer is introduced as an intermediary between the electrode block and the semiconductor chip. This buffer layer absorbs thermal stress generated during pressure-welding and operation, preventing direct transmission of harmful thermal forces to the chip while maintaining electrical contact. The buffer layer acts as a mediator that decouples the thermal and mechanical stress pathways from the electrical conduction pathway.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the interface structure by introducing materials with specific thermal and electrical properties. The buffer layer has parameters optimized to provide thermal stress absorption while maintaining electrical conductivity, effectively changing the stress distribution parameters in the pressure-welded joint.
2Reliability
If pressure-welding is applied to maintain electric contact under high voltage and large current, then power density and reliability are improved, but electrical contact failures occur
Solution Approach 1:
The buffer layer serves as an intermediary that ensures stable electrical contact by accommodating dimensional variations and preventing direct mechanical stress transmission to the electrical contact interface. This intermediary structure maintains consistent electrical pathways while absorbing mechanical disturbances.
Solution Approach 2:
The buffer layer provides beforehand cushioning by being pre-positioned between the electrode block and semiconductor chip to absorb and distribute mechanical stress before it can reach the electrical contact interfaces. This preventive cushioning protects against contact failures during operation.
3Power
If wiring density is increased to improve power density, then device performance is improved, but risk of electrical shorts increases
Solution Approach 1:
The patent transitions from planar wiring arrangements to three-dimensional wiring structures with multiple layers. By stacking wirings in different spatial dimensions and using vertical insulating films, the design achieves higher power density while maintaining adequate insulation distances through the third dimension (vertical spacing between layers).
Solution Approach 2:
The wiring structure is segmented into multiple isolated conductive paths separated by insulating films. This segmentation prevents electrical shorts by creating distinct, electrically isolated channels for current flow, allowing higher wiring density without compromising insulation reliability.
Data Source
AI summary
A semiconductor chip includes a semiconductor substrate, a plurality of first wirings extending in a first direction parallel to the upper surface of the semiconductor substrate and disposed entirely above the upper surface of the semiconductor substrate, a second wiring disposed between two of the first wirings that are adjacent to each other and entirely below the upper surface of the semiconductor substrate such that an upper surface of the second wiring is below a lower surface of the two first wirings, and a first insulating film provided on the second wiring and spaced apart from the two first wirings in a second direction that is perpendicular to the first direction, the first insulating film having an upper surface that is above the lower surface of the two first wirings.