Chipkill Recovery With Split ECC Decoding for Non-Blocking Reads
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Solution Overview
Problem
Existing chipkill recovery schemes in memory systems are blocking, leading to increased read collision and decreased performance due to the need to transfer all data for a stripe into the ECC engine, which occupies virtual memory and increases ECC decoding traffic.
Innovation Solution
Implement a non-blocking chipkill recovery scheme where decoding is performed partially within the NAND storage using a lightweight decoder, offloading some steps to the SoC memory controller, reducing unnecessary data transfer and ECC decoding traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all data for a stripe is transferred into the ECC engine for decoding, then chipkill recovery can be performed, but read collision increases and performance decreases
Solution Approach 1:
The patent divides the decoding process into two segments: a lightweight decoder in the NAND storage device handles initial decoding, and only failed codewords are transferred to the ECC engine in the SoC memory controller. This segmentation allows chipkill recovery to proceed without transferring all stripe data, reducing read collision and maintaining performance.
Solution Approach 2:
The patent extracts the initial decoding function from the ECC engine and places it in the NAND storage device itself. By taking out this function, the system avoids the need to transfer all data to the ECC engine, thereby reducing the blocking effect and improving read performance while maintaining recovery capability.
2Loss of substance
If a lightweight decoder is used in NAND storage, then data transfer volume is reduced, but decoding capability is limited
Solution Approach 1:
The patent applies partial action by using a lightweight decoder that performs only the necessary initial decoding in the NAND storage device. This partial decoding capability is sufficient to handle most cases, and only when decoding fails does the system activate the full ECC engine, avoiding excessive data transfer while maintaining adequate reliability.
Solution Approach 2:
The lightweight decoder acts as an intermediary between the data storage and the full ECC engine. It handles preliminary decoding tasks and only passes failed codewords to the ECC engine, serving as a mediator that reduces data transfer volume while preserving the ability to handle complex error correction when needed.
3Reliability
If decoding is performed entirely in SoC memory controller, then decoding capability is maximized, but ECC decoding traffic increases
Solution Approach 1:
The patent extracts the initial decoding function from the SoC memory controller and relocates it to the NAND storage device. This extraction significantly reduces the amount of data that needs to be transferred to the ECC engine, thereby reducing ECC decoding traffic and the harmful effects associated with high traffic volume while maintaining adequate decoding capability.
Solution Approach 2:
The NAND storage device performs self-service by executing the lightweight decoder locally within the storage medium itself, without requiring constant intervention or data transfer to the SoC memory controller. This self-service capability reduces the burden on the ECC engine and minimizes decoding traffic while still providing comprehensive error correction when needed.
Data Source
AI summary
A memory system and a method for decoding of one or more codewords. The system has a storage medium having therein a first decode, a first processor associated with the storage medium and configured to XOR results obtained from the first decoder when the one or more codewords in the storage medium are decoded, and a memory controller having therein a second decoder and a buffer, the memory controller configured to XOR results obtained from the second decoder. The second decoder decodes the one or more codewords after failure of the first decoder to decode the one or more codewords.