Redundant Data Error Correction TRIZ Cases
- Recovery Log Checksum Validation for Backup Data Integrity
Checksum checks on recovery log data units prevent corruption during backup generation while reducing crash-recovery data loss.
- Read Data Path With Metadata Checks and Parallel Data Recovery
Metadata checks screen read data for errors, trigger RAID-style recovery, and let other reads proceed in parallel to limit latency.
- HRPNC Checksum Encoding for Stable Offline Data Transfer
Enforced checksums modify binary data before HRPNC encoding, improving integrity during manual or unstable offline transfer.
- Memory Read Verification Using Physical-Address Descrambling
Physical-address seeded descrambling and CRC expose memory misreads that LBA checks can miss, improving storage data integrity.
- Selective Codeword Scanning for Faster Memory Page Error Checks
Scanning only a subset of memory page codewords cuts media scan time and resource use while flagging pages that need full ECC error review.
- Memory Controller Decoding for Error Intersection Correction
When standard ECC fails on concentrated errors, the controller locates code intersections and modifies symbols to recover nonvolatile memory data.
- Daisy-Chained Memory Subsystems for Scalable Bandwidth and Capacity
A serially chained memory architecture removes intermediate switches to scale storage capacity, improve bandwidth use, and cut interconnect power.
- DDR6 Memory ECC Layout for Die Failures and Metadata Bits
A 40-bit ECC layout combines SEC, SECDED, and Reed-Solomon coding to protect DDR6 data, detect die failures, and preserve metadata storage.
- Distributed Storage I/O Continuity Across Site Link Failures
Update records and bitmaps let a primary storage site keep I/O running during link failures, then rebuild detached mirrored sites.
- Memory Read Retry Selection by NAND Area Reliability
A controller switches between shift-read and tracking-based retry paths by NAND area reliability to cut read latency without sacrificing read success.
- Shared Storage Chip Layout for User Data and Check Data
By sharing chip space for user data and check data, this case increases usable storage capacity while preserving error detection and correction.
- DRAM In-Line ECC Cache for Lower-Cost Reliable Memory Access
Interleaved ECC in the DRAM array with a local ECC cache cuts extra signals, board area, and power while preserving reliable memory access.
- Persistent Memory Relative Mapping with Floating Offset Metadata
A floating offset in persistent memory metadata lets BIOS remap memory regions after boot-time configuration changes without data loss.
- Memory Array Column Planes for Single-Pass Metadata and Parity Access
By placing metadata and ECC parity across non-selected and extra column planes, memory retrieves the full codeword in one pass with lower latency and power.
- Distributed XOR Protection for UECC Recovery in Nonvolatile Memory
Distributed XOR data across memory planes enables local recovery of UECC user data when ECC and a first XOR path both fail.
- SAT Bad Block Mapping for UECC Jumboblock Reads
Maps UECC jumboblocks to a designated bad block in the SAT, avoiding extra scans and reducing read timeouts in storage controllers.
- Column Plane Memory Layout for Single-Pass ECC and Metadata Retrieval
Parallel column planes fetch data, metadata, and ECC parity in one pass, reducing DRAM access latency and power from repeated reads.
- Memory Auxiliary Data Layout for Low-Latency Error Protection
Distributed auxiliary data lets memory fetch only needed protection bits, cutting secondary accesses while preserving error correction.
- Memory Data Path Parity Using ECC Bits to Cut Latency
Reusing ECC parity bits for data path protection cuts logic operations, latency, and chip area while preserving transfer accuracy.
- Memory Controller Parity Allocation for Burst Error Tolerance
Partial parity blocks are split and placed across continuous memory addresses to spread burst errors and improve nonvolatile data protection.
- Distributed RAID Journaling for Write-Hole Recovery
Non-volatile journal records across RAID drives preserve incomplete writes, replay parity updates after crashes, and avoid a single journal bottleneck.
- DRAM Internal ECC Access Using DMI Pins for Masked Writes
Internal DRAM ECC uses DMI pins and separate CRC access to preserve masked writes while reducing RAID recovery overhead.
- NAND Program Failure Handling for Low-Latency Write Recovery
By moving valid data, marking an uncorrectable error, and deferring RAIN repair, the memory system preserves integrity without stalling writes.
- Select Gate Scanning Using Probabilistic Read Sampling
Random window-based read sampling flags memory portions for select gate scans, reducing latency and read-count tracking overhead.
- Destination Block Stripe Selection for Low-Error Media Management
Preselecting an XLC destination block stripe cuts voltage-shift errors during valid-data relocation without SLC caching or BFEA delays.
- Flash Memory Controller Decoding Using Collaborative 4 KB Codewords
Collaborative 4 KB codewords let a flash memory controller decode small reads faster while reusing successfully decoded data to recover failed codewords.
- NAND Memory Parity Generation for Garbage Collection Bottlenecks
Threshold-triggered parity generation cuts parity buffer demand and swap operations during NAND flash garbage collection while preserving data protection.