Read Data Path With Metadata Checks and Parallel Data Recovery
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Solution Overview
Problem
As memory devices increase in density, data bit errors become increasingly likely, leading to unreliable data returns that can adversely affect computing device performance, and existing data paths provide little opportunity for reliability checks without increasing latency.
Innovation Solution
Implement a read data path with backend data return logic that includes a reliability check using metadata, discarding erroneous data and recovering corrupted data through logical combinations within RAID stripes, allowing parallel data recovery to minimize latency impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased, then storage capacity is improved, but data bit errors become more likely and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by performing reliability checks on data immediately upon retrieval from memory, before the data is used by the processor. The backend data return logic includes error detection and correction mechanisms that activate automatically when data is read from high-density memory, preventing erroneous data from propagating to the processor. This preliminary verification approach maintains data reliability without requiring retransmission or retry operations.
2Reliability
If reliability checks are added to the data path, then data reliability is improved, but latency increases
Solution Approach 1:
The patent introduces an intermediary component - the backend data return logic - that acts as a mediator between the memory array and the processor. This intermediary performs reliability checks, error correction, and data validation functions, filtering out erroneous data before it reaches the processor. By placing the reliability check mechanism in this intermediary position within the data path, the system achieves thorough verification without forcing the processor to wait for multiple retry cycles, thus minimizing latency impact.
3Reliability
If error correction mechanisms are implemented, then data reliability is improved, but bandwidth is reduced
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the level of error correction applied based on the specific data conditions and error patterns detected. The backend data return logic analyzes error characteristics and selectively applies different correction strategies - sometimes requiring full redundancy checks, other times using lighter verification methods. This adaptive approach to error correction maintains high data reliability while optimizing bandwidth utilization by avoiding unnecessary verification overhead for error-free data paths.
Data Source
AI summary
Described apparatuses and methods relate to a read data path for a memory system. The memory system may include logic that receives data and associated metadata from a memory. The logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. If the data is determined not to include an error, the data may be transmitted to a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the data. This may reduce a likelihood the memory system returns corrupted data to a requestor. The memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. In some cases, the data recovery process may involve one or more techniques related to redundant array of disks (RAID) technology.