Memory Controller Parity Allocation for Burst Error Tolerance
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Solution Overview
Problem
Memory systems face challenges in effectively handling burst errors, where errors concentrate on continuous locations on storage media, leading to inadequate protection of data stored in nonvolatile memories.
Innovation Solution
A memory system and control method that generates multidimensional error correction codes, dividing parity into partial parities and allocating them to nonvolatile memory addresses to enhance burst error tolerance, using a memory controller to manage encoding and decoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction encoding is applied to protect data in nonvolatile memories, then data reliability is improved, but burst error tolerance remains insufficient because errors concentrate on continuous locations
Solution Approach 1:
The patent divides the storage medium into multiple code blocks, each protected by a separate error correction code. This segmentation ensures that burst errors affecting continuous locations are distributed across multiple independent code blocks, preventing a single error correction code from being overwhelmed by concentrated errors. The memory controller manages multiple code blocks with different error correction codes, allowing selective decoding based on error detection.
Solution Approach 2:
The patent applies different error correction codes to different code blocks based on their specific error characteristics. The memory controller detects errors in each code block and selects appropriate error correction codes for decoding, allowing localized adaptation to burst error patterns. This enables optimized error correction for each region rather than using a uniform approach.
2Object-affected harmful factors
If diverse functions are proposed to prevent errors from concentrating on some codewords, then burst error tolerance is improved, but device complexity increases
Solution Approach 1:
The memory controller is designed to manage multiple code blocks and perform multiple functions: error detection, error correction code selection, and coordinated decoding. This multi-functional approach consolidates what would otherwise require separate dedicated circuits, reducing overall device complexity while maintaining enhanced burst error tolerance through flexible software-based error correction management.
Data Source
AI summary
A memory controller generates Mi codewords each including a parity with a size Ni, divides each of the parities of the Mi codewords into K partial parities, determines K×A codewords from Mi codewords for Mi write information and the K or less partial parities of the K×A codewords, selects partial parities from the K×A codewords, generates Mi write information including the selected partial parities, and allocates continuous addresses of the nonvolatile memory to the K or less partial parities included in each of the Mi write information. A number of write information with sizes of the included partial parities matched becomes larger.