Memory Data Path Parity Using ECC Bits to Cut Latency
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Solution Overview
Problem
Existing memory systems face increased latency and physical area requirements due to the extensive logical operations involved in data path protection parity operations, which are necessary for ensuring data reliability and security.
Innovation Solution
Performing data path protection parity operations using Error Correction Code (ECC) parity bits generated during ECC operations, reducing the number of logical operations required to generate the DPP parity bit, and incorporating an additional logical operation with a Single Error Correction (SEC) bit to ensure accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data path protection parity operations are performed using traditional methods, then data reliability and security are ensured, but latency increases and physical area requirements increase
Solution Approach 1:
The patent merges the data path protection parity operation with the existing ECC operation by using the same logical operation circuitry and ECC parity bits generated during ECC operations. This integration allows the DPP parity bit to be generated as a byproduct of the ECC operation, eliminating the need for separate parity calculation circuits and reducing overall latency while maintaining data reliability.
Solution Approach 2:
The ECC operation circuitry is designed to serve multiple functions: it performs both error correction code operations and data path protection parity operations. The same logical operation units that generate ECC parity bits are reused to generate the DPP parity bit, making the system multi-functional and reducing the need for dedicated hardware resources.
2Reliability
If data path protection parity operations are performed using traditional methods, then data reliability and security are ensured, but physical area on the device increases
Solution Approach 1:
The patent merges the data path protection parity operation with the existing ECC operation by using the same logical operation circuitry and ECC parity bits generated during ECC operations. This integration allows the DPP parity bit to be generated as a byproduct of the ECC operation, eliminating the need for separate parity calculation circuits and reducing overall latency while maintaining data reliability.
Solution Approach 2:
The ECC operation circuitry is designed to serve multiple functions: it performs both error correction code operations and data path protection parity operations. The same logical operation units that generate ECC parity bits are reused to generate the DPP parity bit, making the system multi-functional and reducing the need for dedicated hardware resources.
3Loss of time
If the number of logical operations is reduced in DPP parity operations, then latency and physical area are reduced, but data protection accuracy may be compromised
Solution Approach 1:
The patent introduces an intermediary approach where the DPP parity bit is derived from ECC parity bits through additional logical operations with data bits. This intermediary method ensures that the reduced set of operations still produces accurate parity information by strategically selecting which bits to operate on, maintaining data protection accuracy while reducing the total number of operations required.
Data Source
AI summary
Methods, systems, and devices for data path protection in memory systems are described. A memory system may calculate a data path protection (DPP) parity bit to ensure data transferred between the memory system and a host system is accurate. For example, the memory system may perform, as part of an error correction code (ECC) operation, multiple first logical operations on data bits to generate ECC parity bits. In response to generating the ECC parity bits, the memory system may perform, as part of a data path parity operation, multiple second logical operations on the ECC parity bits to generate an intermediate parity bit, where the memory system may perform a third logical operation between a single error correction bit and the intermediate parity bit to generate a DPP parity bit. In such examples, the memory system may output the DPP parity bit to the host system.