NAND Program Failure Handling for Low-Latency Write Recovery
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Solution Overview
Problem
Program failures in non-volatile memory systems, such as NAND devices, lead to increased latency and degraded performance, particularly in applications like automotive SSDs, due to the need to postpone write operations when program failures occur.
Innovation Solution
The memory system identifies program failures, moves valid data to a second block while injecting an uncorrectable error, resumes operations, and performs maintenance later, reducing latency by avoiding prolonged queue postponement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system postpones write operations when program failures occur, then data integrity is maintained, but latency increases and performance degrades
Solution Approach 1:
The patent segments the write operation handling into two independent paths: a fast path that immediately queues write commands without checking for program failures (improving latency), and a separate background maintenance operation that handles program failure resolution (maintaining data integrity). This segmentation allows the system to achieve low latency for normal writes while still ensuring data integrity through periodic maintenance.
Solution Approach 2:
The patent performs preliminary actions by continuously monitoring program failure status and maintaining a separate record of program failures. When a write command is received, the system checks this pre-prepared failure information quickly without postponing the write operation. The actual maintenance operation is performed preliminarily in the background, allowing fast write path while ensuring data integrity.
2Reliability
If the memory system postpones write operations to handle program failures, then data integrity is ensured, but productivity decreases
Solution Approach 1:
The patent divides the write operation processing into a high-speed main path that accepts write commands immediately (maintaining productivity) and a separate background maintenance path that handles program failure resolution. This segmentation ensures that normal write operations are not blocked by program failure handling, thus maintaining high throughput while data integrity is preserved through the separate maintenance operation.
Solution Approach 2:
The patent maintains continuous write operations by not interrupting the write command queue even when program failures are detected. The useful action of writing data continues uninterrupted in the fast path, while program failure handling occurs continuously in the background through separate maintenance operations, ensuring both productivity and data integrity.
3Reliability
If the memory system performs immediate maintenance operations on blocks with program failures, then data integrity is maintained, but system performance degrades due to operation postponement
Solution Approach 1:
The patent performs preliminary monitoring and recording of program failures without immediately executing maintenance operations. The system preliminarily identifies and records program failure status, then allows write operations to proceed in the fast path. Maintenance operations are performed preliminarily in the background at convenient times, resolving program failures without blocking the main write path and thus maintaining system performance.
Solution Approach 2:
The patent introduces an intermediary mechanism - a separate background maintenance operation thread - that mediates between the fast write path and program failure handling. This intermediary allows the main write operations to proceed without interruption while simultaneously handling program failure resolution, thus maintaining both data integrity and system performance without direct conflict between the two functions.
Data Source
AI summary
Methods, systems, and devices for program failure handling in non-volatile memory systems are described. The memory system may identify a program failure associated with writing data to a first address of a first block of memory cells. The memory system may move data from the first block to a second block of memory cells based on identifying the program failure at the first address. The memory system may alter the data stored to the second block to include an uncorrectable error after moving the data from the first block. The memory system may perform a redundant array of independent NAND (RAIN) operation on the altered data stored to the second block. In some examples, the RAIN operation may include correcting the uncorrectable error stored to the second block and moving the data from the second block to a third block of memory cells.