DRAM In-Line ECC Cache for Lower-Cost Reliable Memory Access
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Solution Overview
Problem
Conventional DRAM devices require additional components and extra DRAM bus interface signals for error correction code (ECC) protection, increasing cost, board area, and power consumption.
Innovation Solution
In-line error correction code (ECC) circuitry stores ECC data interleaved with user data in the same DRAM array, using an ECC cache to locally manage ECCs without accessing the memory device for consecutive memory addresses, reducing the need for additional components and bus interface signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM devices use additional components and extra DRAM bus interface signals for ECC protection, then error detection and correction capability is improved, but cost, board area, and power consumption increase
Solution Approach 1:
The patent merges the ECC data storage with the user data storage by interleaving ECC bits within the same DRAM array locations, eliminating the need for separate ECC storage components and reducing bus interface complexity while maintaining full ECC protection capability
Solution Approach 2:
The DRAM array is designed to serve dual purposes: storing both user data and ECC data in the same physical locations. The memory controller is enhanced to perform both data access and ECC operations, making the system more universal and reducing overall component count
2Reliability
If conventional DRAM devices use additional components and extra DRAM bus interface signals for ECC protection, then error detection and correction capability is improved, but board area increases
Solution Approach 1:
The patent combines ECC data and user data into the same DRAM array structure, eliminating the need for separate ECC storage memory chips or additional board space for ECC components, thus reducing overall board area while maintaining ECC functionality
3Reliability
If conventional DRAM devices use additional components and extra DRAM bus interface signals for ECC protection, then error detection and correction capability is improved, but power consumption increases
Solution Approach 1:
The patent consolidates ECC operations within the existing DRAM array and memory controller, eliminating the need for separate ECC processing components that would consume additional power. The interleaved structure allows ECC checks to be performed during normal memory access operations without requiring extra power-intensive dedicated ECC hardware
4Device complexity
If ECC data is stored in-line with user data in the same DRAM array, then device complexity and power consumption are reduced, but ECC processing efficiency may be impacted
Solution Approach 1:
The memory controller is designed to perform ECC operations in parallel with data access operations. ECC codes are generated and stored alongside user data during write operations, and ECC verification is performed concurrently during read operations, eliminating sequential processing delays and maintaining high throughput
Data Source
AI summary
An integrated circuit (IC) device includes processor circuitry configured to output a first memory command having a first memory address, and in-line error correction control (ILECC) circuitry configured to receive the first memory command and output the first memory command to a memory device. The ILECC circuitry includes an error correction code (ECC) cache configured to store a first local ECC associated with the first memory command in a first cache line.