Select Gate Scanning Using Probabilistic Read Sampling

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Solution Overview

Problem

Conventional memory systems face performance and reliability issues due to threshold voltage shifts in select gates, leading to incorrect data reading and increased resource consumption for tracking read counts, which impacts user performance and memory latency.

Innovation Solution

Probabilistically determine memory portions for select gate scanning by generating a random number within a window size and flagging memory portions for scanning, using existing probabilistic read disturb handling counters to reduce resource waste and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read counts are tracked for all memory portions to monitor select gate health, then reliability is improved, but device complexity and resource consumption increase

Engineering Contradiction:
Improveselect gate health monitoringVSAvoidread count tracking infrastructure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements probabilistic sampling where only a subset of memory portions are selected for scanning based on a probability threshold. Instead of tracking all memory portions, the system randomly selects portions with probability P, performing partial monitoring that achieves acceptable reliability while significantly reducing the complexity of read count tracking infrastructure.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If periodic scanning of all memory portions is performed to detect threshold voltage shifts, then reliability is improved, but productivity and latency worsen

Engineering Contradiction:
Improvedata reading accuracyVSAvoidmemory access speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs scanning operations on only a probabilistically selected subset of memory portions rather than all portions. This partial scanning approach maintains sufficient reliability for detecting threshold voltage shifts while reducing the time and resources consumed, thereby improving memory access speed and overall productivity.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements periodic scanning where memory portions are scanned at intervals based on probabilistic selection rather than continuous monitoring. This periodic approach allows the system to balance reliability requirements with productivity needs by performing scans only when necessary according to the probabilistic criteria.

Inventive Principle:
Principle #19Periodic action

3Reliability

If comprehensive monitoring of all memory portions is implemented, then reliability is improved, but loss of time increases

Engineering Contradiction:
Improvememory data integrityVSAvoidscan operation duration
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

By selecting only a probabilistic subset of memory portions for scanning, the system reduces the total number of scan operations required. This partial monitoring approach maintains adequate reliability for detecting threshold voltage shifts while significantly reducing the time consumed by scan operations compared to comprehensive monitoring of all memory portions.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20260037370A1Probablistically determining memory portions for select gate scanning
Publication Date: 2026.02.05 MICRON TECHNOLOGY INC
  • US20260037370A1 patent drawing
  • US20260037370A1 patent drawing
  • US20260037370A1 patent drawing

AI summary

Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.