Memory Controller Decoding for Error Intersection Correction
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Solution Overview
Problem
Existing memory systems face challenges in accurately correcting errors in data stored in nonvolatile memories, particularly when errors concentrate in specific intersections, leading to decoding failures despite the use of conventional error correction codes.
Innovation Solution
A memory system employing a concatenated error correction code structure with a first and second error correction code, where decoding failures trigger additional processing to identify error intersections and modify symbols within these intersections, using techniques like multi-bit flip decoding to enhance accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction codes are used, then decoding can be performed with standard processing, but decoding failures occur when errors concentrate in specific intersections
Solution Approach 1:
The patent segments the error correction process into multiple stages: first error correction code decoding, second error correction code decoding, and an additional stage for handling decoding failures by identifying error intersections and performing targeted symbol modifications. This segmentation allows the system to handle concentrated errors effectively without requiring entirely different decoding algorithms.
Solution Approach 2:
The patent performs preliminary identification of error intersections before attempting final decoding. By first decoding with the second error correction code and identifying where decoding failures occur, the system prepares targeted correction actions in advance, which improves the efficiency of the subsequent first error correction code decoding stage.
2Measurement precision
If additional processing is performed to identify and modify error intersections, then decoding accuracy improves, but processing time and complexity increase
Solution Approach 1:
Instead of applying uniform error correction across the entire data block, the patent identifies specific error intersections where decoding failures occur and applies targeted symbol modifications only to those localized regions. This local quality approach improves decoding accuracy while minimizing the additional processing required compared to exhaustive search methods.
Solution Approach 2:
The patent performs partial error correction by first attempting standard decoding procedures, and only when decoding failures are detected does it activate the additional error intersection identification and modification processing. This partial action approach avoids unnecessary processing time for cases where standard decoding succeeds, while still providing enhanced accuracy when needed.
3Reliability
If concatenated error correction codes with multiple stages are used, then error correction capability is enhanced, but device complexity increases
Solution Approach 1:
The patent implements a nested error correction structure where the second error correction code operates on the output of the first error correction code decoding. This nested arrangement allows multiple layers of error protection to be applied systematically, with each layer addressing different types or patterns of errors, thereby enhancing overall error correction capability while maintaining a structured decoder architecture.
Solution Approach 2:
The patent incorporates feedback mechanisms where the results of second error correction code decoding are used to identify error intersections, which then inform targeted modifications to symbols before re-attempting first error correction code decoding. This feedback loop allows the system to adapt its correction strategy based on actual decoding performance, improving reliability without requiring a completely different decoder structure.
Data Source
AI summary
A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores a concatenated code including a first error correction code and a second error correction code. The memory controller performs, for read information read from the nonvolatile memory, second decoding processing with the second error correction code; if decoding in the second decoding processing fails, performs, for the read information reflecting a correction result of the second decoding processing, first decoding processing with the first error correction code; if decoding in the first decoding processing fails, identifies an intersection of component codes that are in two or more respective different dimensions of the second error correction code and each include an error; and performs modification processing for modifying a symbol in the intersection and further performs the first decoding processing.