DRAM Internal ECC Access Using DMI Pins for Masked Writes
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Solution Overview
Problem
Conventional RAID error correction operations in DRAM-based memory systems increase computational complexity, consume critical SRAM storage and ASIC area, and impact bandwidth and processing speed, while traditional RAID architectures limit the use of certain commands and require resource-intensive recovery protocols.
Innovation Solution
Implementing internal memory ECC operations that enable masked write commands by disabling data transfer using DMI pins, allowing CRC information to be stored and accessed separately, thereby enhancing error correction capabilities and optimizing memory system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RAID error correction operations are implemented in DRAM-based memory systems, then data reliability is improved, but computational complexity increases and SRAM storage consumption increases
Solution Approach 1:
The patent extracts the ECC functionality from the memory controller and implements it directly within the DRAM device itself. The ECC information is stored in the DRAM array alongside user data, and the error correction operations are performed by the DRAM internal logic rather than requiring complex external RAID controllers and SRAM buffers. This extraction reduces the computational complexity and SRAM consumption of the overall system while maintaining data reliability.
Solution Approach 2:
The patent merges the storage of user data and ECC information into a single unified memory array structure. Both data types share the same physical storage resources and access pathways, eliminating the need for separate SRAM storage areas and reducing the overall system complexity. The DRAM device integrates both functions in a single chip, allowing concurrent access and processing.
2Reliability
If conventional RAID error correction operations are implemented, then data reliability is improved, but SRAM storage consumption increases
Solution Approach 1:
The patent merges the storage of user data and ECC information into a single unified memory array structure. Both data types share the same physical storage resources and access pathways, eliminating the need for separate SRAM storage areas and reducing the overall system complexity. The DRAM device integrates both functions in a single chip, allowing concurrent access and processing.
Solution Approach 2:
The patent extracts the ECC functionality from the memory controller and implements it directly within the DRAM device itself. The ECC information is stored in the DRAM array alongside user data, and the error correction operations are performed by the DRAM internal logic rather than requiring complex external RAID controllers and SRAM buffers. This extraction reduces the computational complexity and SRAM consumption of the overall system while maintaining data reliability.
3Reliability
If conventional RAID error correction operations are implemented, then data reliability is improved, but bandwidth and processing speed are impacted
Solution Approach 1:
The patent implements preliminary error detection and correction actions directly within the DRAM device during normal data operations. The ECC information is processed and errors are corrected before data reaches the memory controller, allowing the controller to operate at full speed without needing to perform complex RAID error recovery operations. This preliminary action eliminates bandwidth bottlenecks associated with external error correction processing.
4Reliability
If traditional RAID architectures are used, then data reliability is improved, but certain commands are limited and resource-intensive recovery protocols are required
Solution Approach 1:
The patent implements self-service error correction where the DRAM device autonomously detects and corrects errors using its internal ECC logic without requiring external intervention from the memory controller or host system. The device automatically manages its own error recovery, eliminating the need for resource-intensive RAID recovery protocols and providing full command flexibility. The DRAM chip independently handles error correction operations, freeing the memory controller to execute any desired commands.
Data Source
AI summary
In some implementations, a memory system may retrieve, via a first access operation, a block of user data that is stored in a first portion of a memory associated with one or more data pins, wherein internal memory error correction code (ECC) information associated with the block of user data is stored in a second portion of the memory associated with one or more data mask inversion (DMI) pins, and wherein data transfer via the one or more DMI pins is disabled to enable masked write commands. The memory system may retrieve, via a second access operation, cyclic redundancy check (CRC) information that is stored in a third portion of the memory associated with the one or more data pins. The memory system may determine, using the block of user data and the CRC information, whether the block of user data includes one or more bit errors.