Memory Array Column Planes for Single-Pass Metadata and Parity Access
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Solution Overview
Problem
Existing memory devices face limitations in retrieving error correction information and metadata alongside data without impacting performance, often requiring multiple access passes, which increases latency and power consumption.
Innovation Solution
A semiconductor memory device architecture that stores metadata and error correction parity bits in both data column planes and an extra column plane, allowing for single-pass access of codewords, including data, metadata, and parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metadata and error correction information are stored in the memory array alongside data, then information storage capability is improved, but access latency increases due to requiring multiple access passes
Solution Approach 1:
The memory array is segmented into multiple independent column planes, with at least one dedicated extra column plane for storing metadata and error correction information separate from data column planes. This segmentation allows simultaneous access to data and metadata through parallel column plane operations, eliminating the need for multiple sequential access passes while maintaining enhanced storage capability.
2Quantity of substance
If metadata and error correction information are stored in the memory array, then information storage capability is improved, but power consumption increases due to multiple access passes
Solution Approach 1:
The memory array is segmented into multiple independent column planes, with at least one dedicated extra column plane for storing metadata and error correction information separate from data column planes. This segmentation allows simultaneous access to data and metadata through parallel column plane operations, eliminating the need for multiple sequential access passes and reducing overall power consumption.
Solution Approach 2:
The patent combines data, metadata, and error correction information into a single unified access operation by organizing them across different column planes that can be accessed simultaneously. This merging of access operations into one pass reduces the cumulative power consumption that would result from multiple separate access passes.
3Reliability
If multiple access passes are used to retrieve data, metadata, and error correction information, then data integrity is improved through complete retrieval, but device complexity increases
Solution Approach 1:
The memory array is segmented into multiple independent column planes, with at least one dedicated extra column plane for storing metadata and error correction information separate from data column planes. This segmentation allows simultaneous access to data and metadata through parallel column plane operations, eliminating the need for multiple sequential access passes while maintaining enhanced storage capability.
Data Source
AI summary
Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.