Column Plane Memory Layout for Single-Pass ECC and Metadata Retrieval
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Solution Overview
Problem
Existing memory devices face limitations in retrieving a greater number of bits, including parity and metadata, within a single access pass without incurring latency penalties, particularly in volatile memory like DRAM, where the architecture restricts the maximum number of bits that can be retrieved.
Innovation Solution
Implementing a memory device architecture with data column planes and an extra column plane to store metadata and error correction parity bits, allowing for a single-pass access of codewords by using different column select signals to prefetch data, metadata, and parity bits simultaneously, with optional operational modes to optimize latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory architecture is used to retrieve multiple bits including parity and metadata, then the number of retrievable bits increases, but access latency increases due to multiple access passes
Solution Approach 1:
The memory architecture is segmented into multiple independent column planes (first column plane, second column plane, third column plane) that can be accessed simultaneously. Data bits are distributed across the first and second column planes, while parity and metadata are stored in the third column plane, enabling parallel retrieval of all required bits in a single access pass.
Solution Approach 2:
The patent introduces an additional dimension to the traditional memory architecture by adding a third column plane dedicated to storing parity and metadata. This dimensional expansion allows the system to retrieve data, parity, and metadata simultaneously through parallel column accesses, eliminating the need for sequential multi-pass access.
2Quantity of substance
If traditional memory architecture is used to retrieve multiple bits including parity and metadata, then the number of retrievable bits increases, but power consumption increases due to multiple access passes
Solution Approach 1:
The memory architecture is segmented into multiple independent column planes (first column plane, second column plane, third column plane) that can be accessed simultaneously. Data bits are distributed across the first and second column planes, while parity and metadata are stored in the third column plane, enabling parallel retrieval of all required bits in a single access pass.
Solution Approach 2:
The patent enables continuous useful action by performing data retrieval, parity retrieval, and metadata retrieval in a single uninterrupted access pass. All three column planes are accessed simultaneously in parallel, eliminating the idle time and repeated access operations required by traditional sequential architectures.
3Loss of time
If maximum number of bits are retrieved in single-pass access, then latency is reduced, but the memory architecture complexity increases
Solution Approach 1:
The memory architecture is segmented into multiple independent column planes (first column plane, second column plane, third column plane) that can be accessed simultaneously. Data bits are distributed across the first and second column planes, while parity and metadata are stored in the third column plane, enabling parallel retrieval of all required bits in a single access pass.
Data Source
AI summary
Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.


