Memory Read Retry Selection by NAND Area Reliability

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Solution Overview

Problem

Existing memory systems face challenges in efficiently reading data from nonvolatile memory due to varying cell reliability, leading to increased latency and reduced performance when retry read processes are inefficiently applied across different areas of the memory cell array.

Innovation Solution

The memory system employs a controller that selects among multiple read retry processes with varying average times based on the reliability of the target area, utilizing history value sharing units to optimize read operations by employing infield and outfield processes tailored to specific cell reliability states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If retry read processes are applied uniformly across all areas of the memory cell array, then data can be read from nonvolatile memory, but latency increases and performance decreases due to varying cell reliability

Engineering Contradiction:
Improveread success rateVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the memory cell array into multiple areas with different reliability characteristics and applies different retry read processes to each area. High-reliability areas use standard read operations while low-reliability areas use enhanced retry processes, optimizing both read success rate and latency by matching the read strategy to the local reliability characteristics of each area.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The memory cell array is segmented into multiple distinct areas based on reliability metrics. Each area is independently managed with its own read retry parameters, allowing the system to process different regions with appropriate strategies rather than applying a uniform approach across the entire array.

Inventive Principle:
Principle #1Segmentation

2Reliability

If retry read processes are applied to all areas, then data reading coverage is improved, but system performance decreases due to increased processing time

Engineering Contradiction:
Improvedata reading coverageVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system evaluates reliability characteristics of each memory area and applies retry read processes only where necessary. High-reliability areas bypass retry operations to maintain performance, while low-reliability areas receive targeted retry processing to ensure data reading coverage, thus optimizing the balance between reliability and productivity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of applying retry read processes universally, the system applies them partially only to areas where they are needed based on reliability assessment. This partial action approach ensures adequate data reading coverage for problematic areas while avoiding the performance penalty of applying excessive retry operations to already reliable areas.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If different read retry processes are used for different areas, then read efficiency is improved, but device complexity increases

Engineering Contradiction:
Improveread efficiencyVSAvoidcontroller complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The controller performs preliminary reliability assessment of different memory areas during manufacturing or initial operation and stores this information for later use. This preliminary action allows the system to make informed decisions about which retry processes to apply to which areas, improving read efficiency while managing complexity through pre-computed reliability data.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system incorporates feedback mechanisms that monitor read operations and reliability characteristics of different areas. Based on this feedback, the controller dynamically adjusts which retry processes are applied to which areas, optimizing read efficiency while adapting to changing conditions. The feedback loop helps manage complexity by using actual performance data rather than static configurations.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12554582B2Memory system
Publication Date: 2026.02.17 KIOXIA CORP
  • US12554582B2 patent drawing
  • US12554582B2 patent drawing
  • US12554582B2 patent drawing

AI summary

A memory controller can select a first read retry process having a first average required time when reliability of a target area of a nonvolatile memory on which a read process is to be executed satisfies a criteria, the first read retry process including a shift read operation. The memory controller can select a second read retry process having a second average required time that is longer than the first average required time when the reliability of the target area does not satisfy the criteria, the second read retry processes including a tracking operation that is executed before any one of the plurality of read operations of the shift read operation. The memory controller can execute the selected read retry process.