Chiplet Interface BIST Synchronization Using Preamble Signals
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Solution Overview
Problem
In chiplet technology, process defects in interfaces can affect chip functionality and yield rates, and existing interface tests relying on synchronization circuits and key I/Os are not universal, leading to potential defects in packaged chips.
Innovation Solution
A method for synchronous interface testing using preambles sent through multiple interfaces, allowing chips to start Built-In Self-Test (BIST) independently, without relying on synchronization circuits or key I/Os, ensuring valid test initiation across chiplets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing interface tests rely on synchronization circuits and key I/Os, then test initiation can be coordinated, but the test method is not universal and may miss defects
Solution Approach 1:
The patent extracts the synchronization function from dedicated synchronization circuits and key I/Os, implementing it instead through data transmission protocols using existing interfaces. This removes the dependency on special-purpose hardware components while maintaining test coordination capability, thereby improving universality without sacrificing reliability
Solution Approach 2:
The patent makes existing data interfaces serve dual purposes: both data transmission and test synchronization. By embedding synchronization information within normal data streams, the same interfaces are used for both operational data flow and test initiation, eliminating the need for separate synchronization hardware and achieving universal applicability across different chiplet configurations
2Reliability
If a process defect is introduced to an interface of a chiplet during production and manufacturing, then chip functionality is affected, but defects may not be found in chip test process
Solution Approach 1:
The patent implements preliminary testing actions by initiating BIST tests at the chiplet level before final packaging. This early detection approach allows defects to be identified in individual chiplets during manufacturing, preventing defective chiplets from being assembled into finished products, thereby improving defect detection capability while maintaining productivity
Solution Approach 2:
The patent segments the testing process into independent chiplet-level BIST tests rather than relying solely on final packaged chip testing. By dividing the test into modular unit tests that can be performed on individual chiplets, the system achieves more comprehensive defect detection across multiple production stages, improving both reliability and yield rate
3Productivity
If interface test is performed in chiplet technology, then yield rate can be improved, but synchronous starting of test may fail due to interface faults
Solution Approach 1:
The patent implements feedback mechanisms where chiplets exchange status information through data interfaces to confirm successful test initiation. This feedback loop allows the system to detect and compensate for synchronization issues, ensuring that yield rate improvements from interface testing are not undermined by synchronous starting failures
Solution Approach 2:
The patent employs dynamic test initiation where chiplets can adaptively adjust their test starting timing based on real-time interface conditions. Rather than using rigid fixed-time synchronization, the system dynamically coordinates test start times, allowing flexibility to accommodate interface variations and faults while maintaining synchronous operation and preserving yield rate benefits
Data Source
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AI summary
Embodiments of this application provide a method and an apparatus for starting an interface test, and relate to the field of electronic technologies, to synchronously start the interface test at two ends. The method includes: A first chiplet sends a first preamble to a second chiplet through at least one first interface, where the first preamble indicates that the first chiplet is to start a first BIST test, the first chiplet is interconnected to the second chiplet through a plurality of interfaces, and the plurality of interfaces include the at least one first interface; and when the first preamble is completely sent, the first chiplet starts the first BIST test. The second chiplet receives the first preamble from the first chiplet, and detects the first preamble; and when the second chiplet successfully detects the first preamble, the second chiplet starts the first BIST test.