Electronic device
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Solution Overview
Problem
Existing methods for improving computing performance in processors, such as minimizing transistor size, increasing clock frequency, and adding cores, have limitations in efficiency and scalability, particularly in adapting to the semiconductor industry's evolving needs.
Innovation Solution
An electronic device with a heterogeneous architecture incorporating a functional substrate, conductive layer, redistribution-layered substrates, and computing and memory components, utilizing both electrical and optical signals for high-speed communication between components, including optical traces and switching units for flexible signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is minimized to improve computing performance, then more transistors can be arranged compactly, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent divides the processing system into multiple independent cores (first core, second core, third core) with different architectural characteristics. Each core can be manufactured with standard precision while collectively achieving high computing performance through heterogeneous composition rather than minimizing individual transistor size
Solution Approach 2:
Different cores are designed with different architectural qualities suited to specific workloads (e.g., high-performance cores for compute-intensive tasks, efficiency cores for routine tasks). This allows each component to be optimized for its specific function without requiring overall miniaturization that would compromise manufacturing precision
2Productivity
If clock frequency is increased to improve computing performance, then more operations per unit time are achieved, but energy consumption and heat generation worsen
Solution Approach 1:
The system dynamically selects and switches between different cores based on workload requirements. Rather than operating all cores at high frequency continuously, the processor activates only the necessary cores at appropriate frequencies, reducing overall energy consumption while maintaining high performance when needed
Solution Approach 2:
The system changes operational parameters by selecting different core types for different tasks. Efficiency cores handle routine operations at lower frequencies while performance cores handle intensive tasks at higher frequencies, optimizing the balance between computing performance and energy consumption
3Productivity
If the number of cores is increased to improve computing performance, then more parallel processing capability is achieved, but device complexity and communication overhead worsen
Solution Approach 1:
The processing system is segmented into distinct core types with specialized functions. This segmentation allows for manageable complexity by grouping cores into logical units (performance cores, efficiency cores, etc.) rather than treating all cores uniformly, simplifying task scheduling and resource management
Solution Approach 2:
Multiple cores share common resources and infrastructure (cache hierarchy, interconnect, memory controllers). This multi-functionality approach reduces overall device complexity by avoiding duplication of components while still providing parallel processing capability across multiple cores
4Productivity
If chip architecture is improved to enhance collaboration efficiency, then component collaboration is optimized, but manufacturing complexity and adaptability worsen
Solution Approach 1:
The chip architecture uses universal interfaces and standardized communication protocols that allow different core types to collaborate efficiently. This universal design enables high collaboration efficiency while maintaining adaptability, as new core types can be integrated without requiring complete architectural redesign
Solution Approach 2:
The interconnect and cache coherence protocols are designed to dynamically adapt to different core configurations and workload patterns. This dynamic architecture maintains efficient collaboration across heterogeneous cores while being adaptable to future architectural changes and manufacturing variations
Data Source
AI summary
An electronic device includes a functional substrate, a conductive layer having a plurality of circuitries on the functional substrate, a plurality of redistribution-layered substrates arranged along one surface of the functional substrate, a plurality of functional components arranged on the functional substrate, and a plurality of computing and memory components arranged on one side of the redistribution-layered substrate.