Chiplet Interconnect Path Switching for Communication Failures

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Solution Overview

Problem

Communication failures such as disconnection and performance degradation occur between chiplets in semiconductor devices, leading to inefficiencies in information transmission and reception.

Innovation Solution

An electronic device with a system bus and switch logic that dynamically changes transfer paths between chiplets in response to communication failures, using interconnect modules and interfaces to reroute data and control signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If chiplets are connected through interconnect interfaces to enable communication, then information transmission capability is improved, but communication failure risk increases due to potential disconnections and performance degradation

Engineering Contradiction:
Improveinformation transmission capabilityVSAvoidcommunication reliability
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The system dynamically switches between different interconnect interfaces (first and second interconnect interfaces) based on communication status. When communication failure is detected on one interface, the system automatically activates an alternative interface, making the transfer path dynamic and adaptive to changing conditions, thereby resolving the contradiction between maintaining information transmission capability and ensuring communication reliability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters by switching between multiple interconnect interfaces with different characteristics. By monitoring communication performance parameters and switching interfaces based on these parameter changes, the system maintains reliable information transmission even when one interface degrades, thus resolving the contradiction between transmission capability and reliability

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple interconnect interfaces are provided for redundancy, then communication reliability is improved, but device complexity increases

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidinterconnect structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system segments the interconnect functionality into multiple independent interfaces (first and second interconnect interfaces), each capable of operating autonomously. This segmentation allows redundancy without requiring a completely redundant system, reducing overall complexity while maintaining reliability through selective activation of interfaces based on communication needs and status

Inventive Principle:
Principle #1Segmentation

3Productivity

If transfer paths are dynamically changed in response to communication failures, then system performance is maintained, but control complexity increases

Engineering Contradiction:
Improvesystem performanceVSAvoidcontrol logic complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements feedback mechanisms where communication status is continuously monitored and fed back to the control logic. Based on this feedback, the system automatically adjusts the transfer path by switching between interconnect interfaces. This feedback-driven approach maintains system performance while keeping control logic complexity manageable through rule-based switching rather than complex real-time optimization

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12572493B2Electronic device having a plurality of chiplets
Publication Date: 2026.03.10 REBELLIONS INC
  • US12572493B2 patent drawing
  • US12572493B2 patent drawing
  • US12572493B2 patent drawing

AI summary

Provided is an electronic device, including a first chiplet including a system bus, a first interconnect module, and a second interconnect module, and a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or second interconnect interface connected to the second interconnect module, in which, in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed.