Dielectric-Bonded Chiplet Reset Via for Low Z-Height Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges with large Z-heights and alignment accuracy issues in multi-chip modules due to traditional bonding processes like thermocompression bonding, which limits the scalability of electronic packaging architectures.
Innovation Solution
The use of bondable dielectric interfaces as a reset via layer, bonded using a low-temperature process, allows for precise alignment and minimal Z-height by passing vias through a pair of dielectric layers, improving placement accuracy and reducing module thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional thermocompression bonding is used to connect chiplets, then the bonding process is well-established, but the alignment accuracy is insufficient and z-height cannot be minimized
Solution Approach 1:
The patent changes the bonding parameters by using low-temperature bonding (e.g., 150-250°C) instead of traditional high-temperature thermocompression bonding. This parameter change enables the use of bondable dielectric materials that can be precisely aligned and bonded at lower temperatures, thereby improving alignment accuracy while maintaining process feasibility
Solution Approach 2:
The patent employs composite dielectric materials with specific properties that enable both low-temperature bonding and precise alignment. These bondable dielectric layers are designed with controlled viscosity, outgassing characteristics, and bonding temperature properties that allow for improved manufacturing precision without excessive process complexity
2Length of stationary object
If solder connections are used to connect chiplets to package substrate, then electrical connections are achieved, but the Z-height becomes substantially large (approximately 35 μm or greater)
Solution Approach 1:
The patent extracts the solder connection function from the primary interconnect structure and replaces it with direct dielectric-to-dielectric bonding. By removing the solder layer entirely and using bondable dielectric materials that can be bonded at low temperatures, the Z-height is reduced from approximately 35 μm to much thinner dimensions while maintaining connection reliability through the dielectric bonding interface
Solution Approach 2:
The patent substitutes the mechanical solder bonding system with a dielectric-to-dielectric bonding system. Instead of relying on solder metallurgy and reflow processes, the invention uses controlled dielectric bonding at low temperatures, which eliminates the need for thick solder joints and thereby reduces Z-height while preserving electrical connection functionality
3Ease of operation
If die attach film is used for connections, then flexibility is improved, but thick package side bumps are required to accommodate DAF removal
Solution Approach 1:
The patent eliminates the need for permanent thick package side bumps by using a disposable carrier substrate approach. The carrier with bondable dielectric layers is used temporarily during the bonding process and then removed (released) after bonding is complete. This allows for process flexibility during assembly while avoiding the need for thick permanent structural features like traditional PSBs
Data Source
AI summary
Embodiments described herein include electronic packages. In an embodiment, an electronic package comprises a die and a through substrate via that passes through the die. In an embodiment, the through substrate via is coupled to a backside pad on the die. In an embodiment, a first layer is over the backside pad, where the first layer comprises a first dielectric material. In an embodiment, a second layer is over the first layer, where the second layer comprises a second dielectric material. In an embodiment, a via is through the first layer and the second layer.