CHS Cells Replace GDHS for Memory Channel Power Gating
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Solution Overview
Problem
Current memory designs in ASICs face challenges in reducing the size/area and increasing the density of memory cells/standard logic cells due to the constraints imposed by global distributed head switch (GDHS) cells, which result in wasted space and inefficiencies in power gating.
Innovation Solution
The substitution of GDHS cells with cluster head switch (CHS) cells allows for fine-grain power gating in memory channels, reducing channel width and increasing cell density, while maintaining or improving power delivery efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GDHS cells are used for power gating in memory channels, then power switching capability is provided, but channel width increases and cell density decreases
Solution Approach 1:
The patent divides the power gating function into two levels: global power gating for entire memory banks using GDHS cells, and local power gating for individual memory channels using CHS cells. This segmentation allows each cell type to be optimized for its specific function, with CHS cells being narrower and suitable for channel-level control, thereby reducing the width occupied in memory channels while maintaining comprehensive power gating capability.
Solution Approach 2:
The patent introduces a new dimension of power gating control by adding channel-level granularity to the traditional bank-level power gating. This dimensional expansion in control granularity allows power to be switched at multiple hierarchical levels, enabling finer control without requiring wider channels for single-cell GDHS implementation.
2Reliability
If GDHS cells are used for power gating, then power switching is achieved, but IP core area increases
Solution Approach 1:
By segmenting power gating control into global (GDHS) and local (CHS) levels, the patent eliminates the need for wide GDHS cells in every memory channel. The narrower CHS cells replace GDHS cells in channel headers, reducing the area consumed in memory channels while maintaining power gating functionality through coordinated operation of both cell types.
Solution Approach 2:
The patent applies local quality by using different cell types in different locations: GDHS cells are placed in global control positions for bank-level power gating, while narrower CHS cells are placed in channel headers for local channel-level power gating. This location-specific optimization reduces overall IP core area while maintaining comprehensive power gating coverage.
3Area of moving object
If channel width is reduced to increase density, then cell density increases, but power delivery efficiency may deteriorate
Solution Approach 1:
The patent segments power delivery control into two levels: global power control via GDHS cells that can switch entire memory banks, and local power control via CHS cells that control individual channels. This segmentation allows power to be delivered efficiently at the global level while channels use narrower width for density, with CHS cells providing sufficient local power control without requiring wide channels.
Solution Approach 2:
The CHS cell acts as an intermediary between the global power distribution network and the memory channels. It receives power control signals from global controllers and provides localized power gating at the channel level, mediating between the need for wide power delivery paths and the need for narrow channels to increase density.
Data Source
AI summary
An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.