Compute-in-Memory Binary Multiplier Circuit for Neural Networks
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Solution Overview
Problem
Existing artificial neural networks face inefficiencies in binary computations, particularly in convolutional neural networks, due to the separation of memory and computation units, leading to high energy consumption and accuracy issues in multi-bit operations.
Innovation Solution
A circuit and method for binary computation using a computation circuit with NMOS and PMOS transistors, integrated with a memory cell and an adder, enabling in-memory operations that perform logical operations and add operations directly on bit-lines, reducing energy consumption and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory and computation units are separated in existing neural networks, then device architecture is simplified, but energy consumption increases and computation accuracy deteriorates
Solution Approach 1:
The patent merges memory cells and computation circuits into a unified compute-in-memory structure. Memory cells store binary weights while computation circuits perform logical operations directly on stored data, eliminating the need to transfer data between separate memory and computation units. This integration reduces energy consumption from data movement while maintaining architectural efficiency through standardized cell-circuit coupling.
2Measurement precision
If memory and computation units are separated, then device architecture is simplified, but computation accuracy deteriorates
Solution Approach 1:
The integration of computation circuits directly with memory cells enables precise binary logical operations (AND, OR, NOT) to be performed on stored weight values. The computation circuit uses the memory cell's stored binary state as one input and an external binary input as the other input, producing accurate logical operation results that are fed to adders for multi-bit computation, thereby maintaining high computation accuracy.
Solution Approach 2:
The patent replaces traditional multi-bit digital computation with binary logical operations executed through transistor-level circuit mechanisms. NMOS and PMOS transistors implement logical operations directly on binary data stored in memory cells, substituting complex digital logic with simpler, more accurate physical mechanisms that operate at the transistor level, thereby improving computation accuracy.
3Use of energy by moving object
If in-memory operations are implemented, then energy consumption is reduced, but device complexity increases
Solution Approach 1:
The compute-in-memory unit is segmented into distinct functional components: memory cells for weight storage, computation circuits for binary logical operations, and adders for multi-bit accumulation. This segmentation allows each component to be optimized independently while working together as an integrated system, reducing overall energy consumption through specialized function execution.
Solution Approach 2:
The computation circuit is designed with universal functionality to perform multiple binary logical operations (AND, OR, NOT) by configuring the same circuit structure with different input combinations. This multi-functionality reduces the need for separate dedicated circuits for each operation type, thereby reducing device complexity while enabling in-memory operations.
4Use of energy by moving object
If binary logical operations are performed in-memory, then energy consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent implements binary logical operations using transistor-level mechanisms where NMOS and PMOS transistors directly manipulate binary data stored in memory cells. This physical-level implementation replaces complex digital logic circuits with simpler transistor switching operations, reducing circuit complexity while enabling energy-efficient in-memory computation.
Solution Approach 2:
The computation circuit utilizes parameter changes in transistor conductivity and voltage levels to perform binary logical operations. By controlling gate voltages and leveraging transistor on/off states, the circuit executes logical operations through parameter modulation rather than complex structural arrangements, thereby reducing circuit complexity while maintaining functionality.
Data Source
AI summary
Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.