Computations Using Electromechanical Counter-Type Accumulators TRIZ Cases
- Sequential Proof-of-Work Mining to Limit ASIC Parallelization
A non-parallelisable proof-of-work chain uses sequential computation to curb ASIC advantage, cut energy use, and preserve blockchain consensus.
- Global Number Range Generation via Segmented Block Assignment
Segmenting global number ranges into assigned blocks reduces latency and concurrency issues across distributed software applications.
- Compute-in-Memory Binary Multiplier Circuit for Neural Networks
A compute-in-memory circuit merges memory cells with NMOS and PMOS transistors to perform binary logical operations directly on bit-lines.
- Neural Network Accelerator Signal Detector for Power Reduction
A signal detector converts input signals into flag values to enable processing elements to skip arithmetic operations.
- Sparse Look-Up Table for High Radix Division
Segmented sparse look-up tables reduce circuit size while maintaining division speed.
- Common Factor Mass Multiplication Circuitry for Neural Network Efficiency
A common factor mass multiplier circuit generates partial products once and shares them across multiple operations.
- Processing-Memory Architecture Atomic Read-Modify-Write Logic
Integrated read-modify-write logic performs atomic operations directly within memory units to prevent race conditions and reduce resource consumption.
- Quality Metric Estimation for NP-Hard Combinatorial Scheduling
A combinatorial solver system estimates quality metric values using established functions to guide solution search without full optimization.
- Data Packing for Hard-Wired Multiplier Circuits
FPGA multiplier circuits pack logical operands into physical segments to boost throughput without increasing circuit complexity.