Data Packing for Hard-Wired Multiplier Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Machine learning algorithms, such as deep neural networks, require high computational complexity, making them inefficient on general-purpose CPUs, and existing hardware acceleration techniques do not fully leverage the potential of field programmable gate arrays (FPGAs) for matrix-vector multiplication operations.
Innovation Solution
Implementing data packing techniques for hard-wired multiplier circuits in FPGAs, where logical operands are mapped to specific portions of physical operands with zero padding, allowing a single multiplier block to perform multiple multiplication operations simultaneously, thereby increasing processing speed and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple multiplication operations are performed sequentially on a single multiplier circuit, then the circuit complexity remains low, but the processing speed and throughput are limited
Solution Approach 1:
The patent combines multiple multiplication operations into a single physical multiplier circuit by packing multiple logical operands into fewer physical operands. Specifically, two multiplication operations are performed simultaneously using one multiplier circuit by mapping multiple logical operands to portions of physical operands, thereby increasing throughput without proportionally increasing circuit complexity
Solution Approach 2:
The multiplier circuit is designed to perform multiple functions simultaneously. A single physical multiplier circuit can execute multiple multiplication operations by accepting packed physical operands that contain multiple logical operands, making the circuit multi-functional and capable of handling increased computational workload without requiring additional dedicated hardware for each operation
2Speed
If data packing techniques are applied to increase simultaneous multiplication operations, then processing speed improves, but the mapping and extraction operations increase computational overhead
Solution Approach 1:
The patent segments the physical operands into multiple portions, each containing specific logical operands. The first physical operand is divided into portions containing first and second logical operands, and the second physical operand contains a third logical operand. This segmentation allows the multiplier circuit to process multiple operations simultaneously while maintaining clear organization and reducing the complexity of mapping and extraction operations
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A method is provided that includes providing a hard-wired integer multiplier circuit configured to multiply a first physical operand and a second physical operand, mapping a first logical operand to a first portion of the first physical operand, mapping a second logical operand to a second portion of the first physical operand, and mapping a third logical operand to the second physical operand. The method further includes multiplying the first physical operand and the second physical operand using the hard-wired integer multiplier circuit to provide a multiplication result that includes a first portion including a product of the first logical operand and the third logical operand, and a second portion including a product of the second logical operand and the third logical operand.