Neural Network Accelerator Signal Detector for Power Reduction
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Solution Overview
Problem
Neural network accelerating devices face high power consumption due to frequent arithmetic and read operations, especially in binarized neural networks, which reduces data processing speed and increases energy usage.
Innovation Solution
Incorporating a signal detector that converts input signals into flag signals to determine zero or one-value conditions, allowing processing elements to skip unnecessary arithmetic and read operations, thereby reducing power consumption by minimizing dynamic currents and memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple read operations and arithmetic operations are performed for each MAC operation, then data processing capability is maintained, but power consumption increases and data processing speed reduces
Solution Approach 1:
The signal detector performs preliminary detection of zero and one values in input signals before arithmetic operations. By detecting these special cases in advance, the system can skip unnecessary arithmetic operations, reducing both power consumption and maintaining data processing speed for common cases.
Solution Approach 2:
The processing element skips unnecessary arithmetic operations when the signal detector identifies zero or one values in the input signals. This skipping mechanism reduces the number of operations performed, thereby lowering power consumption while maintaining processing efficiency for typical computational patterns.
2Reliability
If all arithmetic operations are executed, then computational accuracy is maintained, but power consumption increases due to dynamic currents
Solution Approach 1:
The system skips arithmetic operations when input signals are determined to be zero or one, as these operations would not change the computational result. This maintains computational accuracy for necessary operations while eliminating redundant calculations that consume power.
Solution Approach 2:
The signal detector changes the operational parameters by identifying special values (zero and one) in the input signals. This parameter identification enables the processing element to adjust its behavior by skipping operations that would be redundant, thus reducing power consumption without affecting computational accuracy.
3Productivity
If frequent memory read operations are performed, then data availability is maintained, but power consumption increases
Solution Approach 1:
The signal detector performs preliminary detection of zero and one values before memory read operations. When these special values are detected, the system can skip the memory read operation entirely, as the values are already known, thereby reducing power consumption while maintaining data availability when needed.
Solution Approach 2:
The processing element skips memory read operations when the signal detector identifies that the required data is a zero or one value. This reduces the frequency of memory accesses, lowering power consumption associated with memory operations while ensuring data is available when actually needed for computation.
Data Source
AI summary
An accelerating device includes a signal detector that converts a first input signal and a second input signal into a first converted input signal and a second converted input signal, respectively, and that generates a final zero-value flag signal, a first one-value flag signal, and a second one-value flag signal. The accelerating device further includes a processing element (PE) that processes the first converted input signal and the second converted input signal based on the final zero-value flag signal, the first one-value flag signal, and the second one-value flag signal and that skips a first arithmetic operation and a second arithmetic operation when the final zero-value flag signal has a first value. The first value of the final zero-value flag signal indicates that the first input signal, or the second input signal, or both have a value of 0.