Processing-Memory Architecture Atomic Read-Modify-Write Logic

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Solution Overview

Problem

In deep learning applications, repeated mathematical operations such as summation or multiplication consume significant memory resources and interrupt processor tasks, leading to limited capacity and potential delays due to race conditions in multi-threaded processing.

Innovation Solution

The implementation of a processing-memory architecture with integrated Read-Modify-Write (RMW) logic, which performs atomic operations like sum-reduction or product-reduction directly in memory, preventing race conditions and optimizing resource usage by synchronizing operations within the memory unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If repeated mathematical operations are performed using conventional memory-processor architecture, then computation can be performed, but memory resources are consumed significantly and processor tasks are interrupted leading to limited capacity and delays

Engineering Contradiction:

Improvecomputation efficiencyVSAvoidmemory resource consumption

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges the processor and memory into a unified processing-memory architecture where processing elements are directly integrated with memory cells. This allows mathematical operations to be performed within the memory structure itself, eliminating the need for separate memory access cycles and reducing overall memory resource consumption while improving computation efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces specialized processing elements as intermediaries between conventional memory and processors. These processing elements handle mathematical operations locally within the memory structure, acting as mediators that reduce the burden on both main memory and external processors, thereby improving computation efficiency while reducing memory resource consumption.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If multi-threaded processing is used to increase throughput, then more tasks can be processed, but race conditions occur causing delays and reducing reliability

Engineering Contradiction:

Improveprocessing throughputVSAvoidthread safety

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements preliminary synchronization mechanisms within the processing-memory architecture that prepare and coordinate multi-threaded operations before they execute. By pre-establishing synchronization protocols and coordination structures, the system enables high throughput multi-threaded processing while preventing race conditions and ensuring thread safety.

Inventive Principle:

Principle #10Preliminary action

3Ease of operation

If processor tasks are interrupted for memory operations, then data can be accessed, but capacity is limited and delays occur

Engineering Contradiction:

Improvedata access capabilityVSAvoidprocessor delay

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

By merging processing capabilities directly into the memory structure, the patent enables data access and computation to occur simultaneously within the same architectural layer. This eliminates the need for processor interruptions and reduces delays, while maintaining ease of data access through the integrated architecture.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11249724B1Processing-memory architectures performing atomic read-modify-write operations in deep learning systems

Publication Date: 2022.02.15 INTEL OVERSEAS FUNDING CORP

AI summary

A computational apparatus includes a memory unit and Read-Modify-Write (RMW) logic. The memory unit is configured to hold a data value. The RMW logic, which is coupled to the memory unit, is configured to perform an atomic RMW operation on the data value stored in the memory unit.