Circuit Area Recovery via Reverse-Levelized Gate Downsizing
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Solution Overview
Problem
Conventional circuit synthesis approaches face inefficiencies and poor quality results due to their iterative trial-and-error methods, especially when dealing with large circuit designs and multiple timing constraints across various process corners and modes, leading to computationally expensive processes.
Innovation Solution
The proposed solution involves a reverse-levelized processing order for selecting gates for area recovery, where timing margins are propagated backward to optimize gate sizes using closed-form expressions based on logical and parasitic delay models, ensuring no new timing violations are introduced during the downsizing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error approach is used for area recovery, then timing constraints are satisfied, but computation time becomes too long and results are poor quality
Solution Approach 1:
The patent performs preliminary actions by calculating timing margins for all gates before the area recovery process begins. This allows the system to identify which gates can be safely downsized without violating timing constraints, eliminating the need for iterative trial-and-error adjustments and significantly reducing computation time while maintaining timing satisfaction.
Solution Approach 2:
The patent replaces the mechanical iterative trial-and-error optimization process with a analytical approach using timing margin calculations and closed-form expressions. This substitution eliminates repeated computational cycles and provides direct determination of optimal gate sizes, transforming a computationally intensive process into an efficient analytical solution.
2Area of moving object
If iterative optimization process is executed for many iterations, then area is reduced, but computation time increases significantly
Solution Approach 1:
The patent creates a simplified analytical model (copy) of the timing constraints and gate characteristics, allowing direct calculation of optimal sizes without iterative simulation. This model uses timing margins and closed-form expressions to determine gate sizes in a single pass, achieving area reduction without the time cost of repeated optimization cycles.
Solution Approach 2:
The patent changes the approach from iterative adjustment to direct parameter calculation by using closed-form expressions that compute optimal gate sizes based on timing margins. This parameter transformation allows immediate determination of optimal dimensions without repeated trial-and-error iterations, significantly reducing optimization time while achieving the same area reduction.
3Measurement precision
If conventional synthesis tools check timing across many process corners and modes, then timing accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent segments the timing analysis by calculating timing margins for each gate independently based on its specific characteristics and constraints. This segmentation allows the system to handle multiple process corners and modes through systematic calculation rather than exhaustive iterative checking, maintaining timing accuracy while reducing overall computational complexity through structured analysis.
Data Source
AI summary
Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design.