Circuit Board Conductive Bump Protection
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Solution Overview
Problem
The increased demand for higher precision and height of conductive bumps in package-on-package (POP) circuit boards leads to excessive exposure, increasing the risk of oxidation and erosion, which negatively impacts the yield of chip package products.
Innovation Solution
A circuit board design featuring a photo imageable dielectric layer with openings that expose parts of the circuit layer, allowing for the formation of conductive bumps connected to the layer, with the dielectric layer covering the side surfaces of the bumps, and optionally a solder mask layer for additional protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the conductive bumps are increased in height to provide adequate space between chip packages, then the space for accommodating chips is improved, but the side surfaces of the conductive bumps are excessively exposed to external environment increasing oxidation and erosion risk
Solution Approach 1:
The patent introduces a photo imageable dielectric layer as an intermediary substance that fills the spaces between conductive bumps and covers their side surfaces. This dielectric layer acts as a protective mediator that prevents direct exposure of the conductive bumps to the external environment, thereby reducing oxidation and erosion risk while maintaining the required bump height for chip accommodation.
Solution Approach 2:
The photo imageable dielectric layer functions as a protective thin film that conforms to the contours of the conductive bumps. After patterning, this film layer covers the side surfaces of the bumps, providing environmental protection similar to how flexible shells protect internal structures, while allowing the bumps to maintain their necessary height.
2Quantity of substance
If the layout density of conductive bumps is increased to accommodate more I/O terminals, then the I/O capacity is improved, but the manufacturing precision requirement for conductive bumps is enhanced
Solution Approach 1:
The patent applies preliminary action by forming the photo imageable dielectric layer and patterning it with openings before forming the conductive bumps. This pre-established template guides the precise formation of conductive bumps at the correct locations and dimensions, thereby achieving high manufacturing precision and layout density without compromising bump quality.
Solution Approach 2:
The patent replaces traditional mechanical alignment and positioning methods with a photo imaging system. The photo imageable dielectric layer is patterned using optical exposure and development processes, which provide higher precision and repeatability compared to mechanical positioning methods, enabling increased layout density with maintained manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances manufacturing precision and reduces the risk of oxidation and erosion of conductive bumps, thereby improving the yield and reliability of chip package products by minimizing exposure to the external environment.
Implementation Method 1
A plurality of high density and high precision conductive bumps are formed on the substrate at one time through a plurality of openings of a photo imageable dielectric layer
Implementation Method 2
A plurality of conductive bumps are formed on the electrical connection area through the openings, wherein each of the conductive bumps is connected to the first circuit layer
Data Source
AI summary
A circuit board including a substrate, a photo imageable dielectric layer and a plurality of conductive bumps is provided. The substrate has a first surface and a first circuit layer, wherein the first surface has a chip disposing area and an electrical connection area, and the first circuit layer is embedded in the first surface. The photo imageable dielectric layer is disposed on the electrical connection area and has a plurality of openings, wherein parts of the first circuit layer is exposed by the openings. The conductive bumps are disposed at the openings respectively and connected to the first circuit layer, wherein a side surface of each of the conductive bumps is at least partially covered by the photo imageable dielectric layer. In addition, a manufacturing method of the circuit board is also provided.