Circuit Board Dummy Pattern Parasitic Capacitance Control
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Solution Overview
Problem
Thin substrates face limitations in controlling parasitic capacitance due to restricted thickness, which affects the spacing between electrodes and leads to sensitive changes in substrate properties during layer stacking.
Innovation Solution
A circuit board design incorporating a dummy pattern on the via pad and via for power, with the dummy pattern's size adjustable to control parasitic capacitance, implemented on a thin substrate to minimize its influence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of the substrate is reduced to minimize parasitic capacitance, then the substrate properties become more sensitive to capacitance changes, but the spacing between electrodes cannot be maximized
Solution Approach 1:
The patent applies local quality by introducing a dummy pattern only in specific regions where capacitance control is needed, rather than uniformly across the entire substrate. The dummy pattern is positioned adjacent to the via pad to locally adjust the electric field distribution and control parasitic capacitance without affecting the overall substrate thickness or other regions.
Solution Approach 2:
The patent changes the geometric parameters of the via pad by adding a dummy pattern with specific dimensions (smaller than the via pad but larger than the via). This parameter modification allows control of parasitic capacitance by adjusting the area and position of the dummy pattern, enabling capacitance control in thin substrates where traditional thickness-based control is limited.
2Object-affected harmful factors
If build-up layers are added to control capacitance, then capacitance control is achieved, but the substrate thickness increases
Solution Approach 1:
The patent extracts the capacitance control function from the bulk substrate structure and relocates it to a surface-level dummy pattern. Instead of adding layers to control capacitance, the solution removes the need for additional build-up layers by using a planar dummy pattern that provides the same capacitance control effect without increasing substrate thickness.
Solution Approach 2:
The patent transitions from vertical capacitance control (through additional build-up layers increasing thickness) to horizontal capacitance control (through dummy pattern area adjustment on the same plane). This dimensional shift allows capacitance control without compromising the thin substrate requirement.
3Object-affected harmful factors
If the dummy pattern area is increased to control capacitance, then parasitic capacitance is reduced, but the cross-sectional area of the via pad increases
Solution Approach 1:
The dummy pattern is positioned locally adjacent to the via pad rather than expanding the via pad itself. This local placement allows the dummy pattern to control capacitance by creating an additional electric field region without increasing the via pad's cross-sectional area, maintaining the via pad's original electrical connection properties.
Solution Approach 2:
The patent segments the capacitance control function into two separate elements: the via pad for electrical connection and the dummy pattern for capacitance control. This segmentation allows independent optimization of each element's function, where the via pad maintains its original area for signal transmission while the dummy pattern provides capacitance control through its separate geometric configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dummy pattern effectively reduces parasitic capacitance, allowing for better control over capacitance values and design flexibility while maintaining the substrate's electrical properties, even with a thin structure.
Implementation Method 1
properties of the substrate itself are sensitively changed by parasitic capacitance generated at the time of stacking the layers of the substrate and parasitic capacitance generated in a through via
Implementation Method 2
the larger the spaced distance between electrodes formed on the substrate, the smaller the capacitance value
Data Source
AI summary
Disclosed herein is a circuit board including: a base substrate including a via for power and a via pad for power connected to the via for power; and an insulating layer formed on the base substrate and including a dummy pattern formed in a region facing the via pad for power.