Circuit Board Extension Portion Width Variation
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Solution Overview
Problem
The Embedded Trace Substrate (ETS) method for manufacturing circuit boards results in voids in the insulating layer, leading to reduced strength and warpage issues, particularly in regions with low circuit pattern density, which affects the physical and electrical reliability of the circuit board.
Innovation Solution
A circuit board design featuring a first insulating layer with a circuit pattern that includes an extension portion with a varying step portion, where the width increases adjacent to the outer region, and a protective layer with a narrower width than the insulating layer, minimizing voids and warpage by optimizing the lamination process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the ETS method is used to manufacture circuit boards with thin insulating layers, then miniaturization and integration are improved, but voids occur in low-density regions causing warpage and reduced strength
Solution Approach 1:
The patent applies local quality by creating a non-uniform circuit pattern density distribution. Specifically, the outer region adjacent to the plating lead is designed with lower circuit pattern density compared to the central region. This local variation in density prevents void formation during lamination while maintaining overall miniaturization benefits, thereby resolving the contradiction between thin insulating layer and structural integrity.
2Productivity
If circuit patterns are densely formed in the central region to increase integration, then circuit integration is improved, but voids occur in the outer region during lamination
Solution Approach 1:
The patent implements local quality by intentionally creating different circuit pattern densities in different regions. The central region maintains high density for circuit integration, while the outer region adjacent to the plating lead is designed with lower density. This spatial variation in pattern density ensures complete insulating layer filling during lamination without void formation, while preserving high circuit integration in the central area.
3Weight of moving object
If the insulating layer thickness is reduced to achieve thinner circuit boards, then weight reduction is improved, but the region where voids occur is increased
Solution Approach 1:
The patent applies local quality by designing specific regions with optimized circuit pattern densities. The outer region adjacent to the plating lead is configured with lower circuit pattern density, which prevents void formation during lamination. This localized optimization allows the insulating layer to be completely filled even when the overall layer thickness is reduced, thereby enabling weight reduction without increasing void occurrence.
Data Source
AI summary
A circuit board according to an embodiment includes a first insulating layer; a first circuit pattern disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer and having a width narrower than that of the first insulating layer; wherein an upper surface of the first insulating layer includes a first region vertically overlapping with the second insulating layer, and a second region excluding the first region, wherein the first circuit pattern includes an extension portion extending from the first region to the second region; and wherein a width of the extension portion in the second region is greater than a width of at least a part of the extension portion in the first region.