Multi-layer Circuit Board Interposer Conductive Paste Lamination
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Solution Overview
Problem
Existing multi-layer circuit board fabrication methods require multiple lamination steps, leading to inefficiencies such as trace migration during heat and pressure application, and the need for drilling through holes for interconnections, which can cause transmission line reflections and impedance discontinuities.
Innovation Solution
A method involving a dielectric substrate with conductive traces and apertures, an interposer layer with conductive paste-filled apertures, and a single lamination step under elevated temperature and pressure to form a monolithic circuit board, eliminating the need for drilling through holes and preventing trace migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple lamination steps are used to add layers, then electrical connectivity between layers is achieved, but fabrication time increases and trace migration occurs during heat and pressure application
Solution Approach 1:
The patent combines multiple lamination steps into a single lamination operation by stacking all dielectric layers with their respective copper traces and via holes in one assembly, then laminating them simultaneously. This merging of sequential operations into a single parallel process reduces fabrication time while maintaining electrical connectivity between all layers through the via holes that are plated during the same lamination cycle.
2Reliability
If multiple lamination steps are used to add layers, then electrical connectivity between layers is achieved, but trace migration occurs during heat and pressure application
Solution Approach 1:
The patent performs preliminary plating of via holes in each dielectric layer before the final lamination step. This preliminary action ensures that conductive pathways are established within each layer prior to the high-heat lamination process, so that when all layers are laminated together in a single step, the traces are already secured and less prone to migration. The via holes act as anchors that prevent trace displacement during the lamination process.
3Reliability
If through holes are drilled after lamination for interconnections, then layer-to-layer connectivity is achieved, but transmission line reflections and impedance discontinuities occur
Solution Approach 1:
The patent performs preliminary plating of via holes within each dielectric layer before lamination, creating continuous conductive pathways that are integrated into the trace layers. This preliminary formation of via holes and their plating ensures that the electrical connections are established before the final lamination, allowing for controlled impedance design and reducing discontinuities that would occur with post-lamination drilling. The via holes are precisely positioned and plated to maintain transmission line characteristics.
4Device complexity
If sequential lamination of dielectric cores is used, then multi-layer structure is formed, but the number of lamination steps increases with the number of layers
Solution Approach 1:
The patent merges the lamination of multiple dielectric layers into a single lamination operation by preparing all layers with their copper traces and via holes in advance, then stacking them in the desired configuration and laminating them simultaneously. This approach reduces the number of lamination cycles from multiple sequential steps to a single parallel process, significantly improving productivity while maintaining the complex multi-layer structure with all necessary electrical interconnections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a single lamination step, preventing trace migration and providing electrical connectivity between layers, reducing fabrication time and minimizing transmission line reflections and impedance discontinuities.
Implementation Method 1
an elevated temperature is provided sufficient to melt the conductive paste while the layers are laminated together
Implementation Method 2
the layers are laminated together under elevated externally applied mechanical lamination pressure
Data Source
Figure 1A~1C
Figure 2~3
Figure 4~5B
AI summary
A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.