Circuit Board Manufacturing with Sputtered Adhesion Layer

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Solution Overview

Problem

Current methods for manufacturing circuit boards with fine line width/pitch face challenges such as weak adhesion of the circuit pattern layer, leading to instability and distortion, particularly for line widths less than 25 μm, which affects the electrical properties and reliability of the circuit board.

Innovation Solution

A method involving a substrate with a stop layer and a resin layer, where conduction holes are drilled, followed by sequential sputtering, chemical plating, and electroplating processes to form metal layers, ensuring strong adhesion and stability of the circuit pattern, with the resin layer reinforced by materials like glass or carbon fibers to enhance mechanical strength.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the line width/pitch is reduced to increase package density, then the chip connection density is improved, but the circuit pattern becomes unstable and prone to distortion

Engineering Contradiction:
Improvepackage densityVSAvoidcircuit pattern stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the surface roughness parameter of the resin layer from conventional values to a specific range (Ra 0.5-2.0 μm, Rz 2.0-5.0 μm), which optimizes the adhesion between the resin layer and copper foil, preventing circuit pattern distortion even at reduced line widths of 10-20 μm

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses a composite structure consisting of a resin layer with specific surface roughness characteristics combined with copper foil, creating a stable base that maintains circuit pattern integrity during the manufacturing process and prevents short circuits

Inventive Principle:
Principle #40Composite materials

2Manufacturing precision

If the surface roughness of the copper layer is reduced to improve circuit pattern precision, then the line width control is improved, but the adhesion strength between layers is weakened

Engineering Contradiction:
Improveline width controlVSAvoidadhesion strength
Core Design Contradiction:
Manufacturing precisionVSStrength

Solution Approach 1:

The patent optimizes the surface roughness parameters of the resin layer (Ra 0.5-2.0 μm, Rz 2.0-5.0 μm) to provide optimal adhesion strength while maintaining the ability to achieve precise line width control in the resulting circuit pattern

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The resin layer acts as an intermediary between the substrate and the copper circuit pattern, with its controlled surface roughness providing both adequate adhesion strength and a stable base for precise pattern formation

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If the chemical plating process is used to form the circuit pattern layer, then the fine line width/pitch is achieved, but the circuit pattern layer peels off due to weak adhesion

Engineering Contradiction:
Improveline width/pitchVSAvoidadhesion strength
Core Design Contradiction:
Manufacturing precisionVSStrength

Solution Approach 1:

The patent performs preliminary preparation of the resin layer surface by controlling its roughness before the chemical plating process, creating an optimal surface that ensures strong adhesion of the copper circuit pattern layer during and after the plating process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent modifies the surface roughness parameters of the resin layer to specific ranges that maximize adhesion strength during the chemical plating process, preventing peeling while achieving the required fine line width/pitch

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves high precision and reliability for circuit boards with line widths less than 10 μm, improving electrical quality and reducing manufacturing costs while preventing distortion and peeling of the circuit pattern.

Implementation Method 1

a sputtering process for forming a first metal layer on a substrate

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 2

a chemical plating process for forming a second metal layer on the first metal layer

Methodology Applied
Scientific EffectChemical plating: Deposition (physical)

Implementation Method 3

an electroplating process for forming a third metal layer on the second metal layer

Methodology Applied
Scientific EffectElectroplating: Electroplating

Implementation Method 4

a circuit etching process to form an electrical circuit with fine line width/pitch by etching the first and second metal layers

Methodology Applied
Scientific EffectEtching: Ablation

Data Source

PatentUS9744624B2Method for manufacturing circuit board
Publication Date: 2017.08.29 KINSUS INTERCONNECT TECH
  • US9744624B2 patent drawing
  • US9744624B2 patent drawing
  • US9744624B2 patent drawing

AI summary

Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 μm for fine line width/pitch.