Circuit Board Via Structure with Segmented Plating for Thick Dielectrics
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Solution Overview
Problem
Circuit boards with thick dielectric layers used in 5G communication systems face reliability issues due to plating defects and increased surface roughness in via holes, leading to signal loss and potential delamination.
Innovation Solution
Incorporating an additional pad with a predetermined height between the connection portion of the via portion to address plating defects and reducing surface roughness by forming a resin layer on the via hole inner wall to minimize signal loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the dielectric layer thickness is increased to meet antenna requirements, then the antenna performance is improved, but the via reliability deteriorates due to plating defects
Solution Approach 1:
The via structure is segmented into multiple parts: a via hole through the dielectric layer, a connection portion at the bottom, and an additional pad layer. This segmentation allows the plating process to be divided into manageable sections, preventing plating defects that occur in thick continuous vias while maintaining the required dielectric thickness for antenna performance.
Solution Approach 2:
An additional pad is introduced as an intermediary element between the via hole and the upper circuit pattern. This pad serves as a intermediate plating surface that breaks the continuous plating path, allowing for better plating control and reliability in thick dielectric layers without compromising antenna performance.
2Ease of manufacture
If the via hole is formed using physical or chemical methods, then the through hole can be created, but the inner wall roughness increases causing signal loss
Solution Approach 1:
The inner wall of the via hole is treated with a roughness-reducing process before plating. This preliminary action smooths the inner wall surface created by physical or chemical drilling, reducing the roughness that would otherwise cause signal loss in high-frequency applications while maintaining the ease of via hole formation.
Solution Approach 2:
The surface roughness parameter of the via hole inner wall is changed through additional processing steps. By controlling and reducing the roughness parameter after hole formation but before plating, the signal loss is minimized while maintaining the manufacturing simplicity of physical or chemical drilling methods.
3Reliability
If plating is performed on thick dielectric layers, then via connection is achieved, but plating defects occur reducing reliability
Solution Approach 1:
The plating process is segmented by introducing an additional pad that divides the continuous plating path into separate sections. This allows each section to be plated with better control over plating thickness and quality, preventing defects that occur in thick continuous vias while maintaining connection reliability.
Solution Approach 2:
The additional pad acts as an intermediary plating surface that breaks the long plating path into shorter segments. This intermediary structure allows for better plating solution penetration and more uniform plating deposition, improving plating quality and reducing defects in thick dielectric layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of the circuit board by preventing plating defects and minimizing signal loss, making it suitable for high-frequency applications.
Implementation Method 1
forming a resin layer on the via hole inner wall to minimize signal loss
Implementation Method 2
the via is formed by plating after forming a through hole in one side surface of the substrate including the circuit pattern
Data Source
AI summary
A circuit board according to an embodiment includes an insulating layer; and a via portion disposed in a via hole formed in the insulating layer; wherein the via portion includes: a first pad disposed on a lower surface of the insulating layer; a second pad disposed on an upper surface of the insulating layer; a third pad disposed in the via hole and disposed on the first pad; and a connection portion disposed in the via hole and disposed between the second pad and the third pad.